Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it. Add macros to make inlines for reading/writing co-processor registers.
This commit is contained in:
matt
parent
312c339026
commit
977dafe551
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.84 2012/08/14 20:39:49 matt Exp $ */
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/* $NetBSD: cpu.c,v 1.85 2012/08/29 17:44:25 matt Exp $ */
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/*
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* Copyright (c) 1995 Mark Brinicombe.
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@ -46,15 +46,16 @@
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#include <sys/param.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.84 2012/08/14 20:39:49 matt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.85 2012/08/29 17:44:25 matt Exp $");
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/proc.h>
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#include <sys/conf.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/kmem.h>
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#include <sys/proc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/cpu.h>
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#include <arm/cpuconf.h>
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#include <arm/undefined.h>
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@ -66,45 +67,94 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.84 2012/08/14 20:39:49 matt Exp $");
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char cpu_model[256];
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#ifdef MULTIPROCESSOR
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volatile u_int arm_cpu_hatched = 0;
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u_int arm_cpu_max = 0;
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uint32_t arm_cpu_mbox __cacheline_aligned = 0;
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uint32_t arm_cpu_marker __cacheline_aligned = 1;
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#endif
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/* Prototypes */
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void identify_arm_cpu(device_t dv, struct cpu_info *);
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void identify_cortex_caches(device_t dv);
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void identify_features(device_t dv);
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/*
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* Identify the master (boot) CPU
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*/
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void
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cpu_attach(device_t dv)
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cpu_attach(device_t dv, cpuid_t id)
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{
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int usearmfpe;
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struct cpu_info *ci;
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usearmfpe = 1; /* when compiled in, its enabled by default */
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if (id == 0) {
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ci = curcpu();
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curcpu()->ci_dev = dv;
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/* Get the CPU ID from coprocessor 15 */
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evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC,
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NULL, dv->dv_xname, "arm700swibug");
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/* Get the CPU ID from coprocessor 15 */
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curcpu()->ci_arm_cpuid = cpu_id();
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curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK;
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curcpu()->ci_arm_cpurev =
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curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK;
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identify_arm_cpu(dv, curcpu());
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if (curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
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curcpu()->ci_arm_cpurev < 3) {
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aprint_normal("%s: SA-110 with bugged STM^ instruction\n",
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dv->dv_xname);
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ci->ci_arm_cpuid = cpu_id();
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ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK;
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ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK;
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} else {
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#ifdef MULTIPROCESSOR
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KASSERT(cpu_info[id] == NULL);
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ci = kmem_zalloc(sizeof(*ci), KM_SLEEP);
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KASSERT(ci != NULL);
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ci->ci_cpl = IPL_HIGH;
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ci->ci_cpuid = id;
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ci->ci_data.cpu_core_id = id;
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ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq;
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ci->ci_arm_cpuid = cpu_info_store.ci_arm_cpuid;
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ci->ci_arm_cputype = cpu_info_store.ci_arm_cputype;
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ci->ci_arm_cpurev = cpu_info_store.ci_arm_cpurev;
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cpu_info[ci->ci_cpuid] = ci;
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if ((arm_cpu_hatched & (1 << id)) == 0) {
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ci->ci_dev = dv;
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dv->dv_private = ci;
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aprint_naive(": disabled\n");
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aprint_normal(": disabled (unresponsive)\n");
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return;
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}
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#else
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aprint_naive(": disabled\n");
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aprint_normal(": disabled (uniprocessor kernel)\n");
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return;
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#endif
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}
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ci->ci_dev = dv;
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dv->dv_private = ci;
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evcnt_attach_dynamic(&ci->ci_arm700bugcount, EVCNT_TYPE_MISC,
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NULL, device_xname(dv), "arm700swibug");
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#ifdef MULTIPROCESSOR
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/*
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* and we are done if this is a secondary processor.
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*/
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if (!CPU_IS_PRIMARY(ci)) {
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aprint_naive(": %s\n", cpu_model);
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aprint_normal(": %s\n", cpu_model);
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mi_cpu_attach(ci);
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return;
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}
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#endif
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identify_arm_cpu(dv, ci);
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#ifdef CPU_STRONGARM
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if (ci->ci_arm_cputype == CPU_ID_SA110 &&
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ci->ci_arm_cpurev < 3) {
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aprint_normal_dev(dv, "SA-110 with bugged STM^ instruction\n");
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}
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#endif
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#ifdef CPU_ARM8
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if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) {
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if ((ci->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) {
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int clock = arm8_clock_config(0, 0);
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char *fclk;
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aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock);
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aprint_normal_dev(dv, "ARM810 cp15=%02x", clock);
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aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : "");
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aprint_normal("%s", (clock & 2) ? " sync" : "");
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switch ((clock >> 2) & 3) {
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@ -150,6 +200,7 @@ cpu_attach(device_t dv)
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*/
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int usearmfpe = 1;
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if (boot_args)
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get_bootconf_option(boot_args, "armfpe",
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BOOTOPT_TYPE_BOOLEAN, &usearmfpe);
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@ -493,12 +544,11 @@ static const char * const wtnames[] = {
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void
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identify_arm_cpu(device_t dv, struct cpu_info *ci)
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{
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u_int cpuid;
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enum cpu_class cpu_class = CPU_CLASS_NONE;
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int i;
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const u_int cpuid = ci->ci_arm_cpuid;
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const char * const xname = device_xname(dv);
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const char *steppingstr;
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cpuid = ci->ci_arm_cpuid;
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int i;
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if (cpuid == 0) {
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aprint_error("Processor failed probe - no CPU ID\n");
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@ -521,10 +571,19 @@ identify_arm_cpu(device_t dv, struct cpu_info *ci)
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if (cpuids[i].cpuid == 0)
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sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid);
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aprint_naive(": %s\n", cpu_model);
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aprint_normal(": %s\n", cpu_model);
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if (ci->ci_data.cpu_cc_freq != 0) {
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char freqbuf[8];
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humanize_number(freqbuf, sizeof(freqbuf), ci->ci_data.cpu_cc_freq,
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"Hz", 1000);
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aprint_normal("%s:", dv->dv_xname);
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aprint_naive(": %s %s\n", freqbuf, cpu_model);
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aprint_normal(": %s %s\n", freqbuf, cpu_model);
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} else {
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aprint_naive(": %s\n", cpu_model);
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aprint_normal(": %s\n", cpu_model);
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}
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aprint_normal("%s:", xname);
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switch (cpu_class) {
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case CPU_CLASS_ARM6:
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@ -573,26 +632,33 @@ identify_arm_cpu(device_t dv, struct cpu_info *ci)
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aprint_normal("\n");
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#ifdef CPU_CORTEX
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if (CPU_ID_CORTEX_P(cpuid)) {
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identify_cortex_caches(dv);
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if (0)
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identify_features(dv);
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} else
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#endif
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/* Print cache info. */
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if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0)
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goto skip_pcache;
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if (arm_picache_line_size != 0 || arm_pdcache_line_size != 0) {
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if (arm_pcache_unified) {
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aprint_normal_dev(dv, "%dKB/%dB %d-way %s unified cache\n",
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arm_pdcache_size / 1024,
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arm_pdcache_line_size, arm_pdcache_ways,
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wtnames[arm_pcache_type]);
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} else {
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aprint_normal_dev(dv, "%dKB/%dB %d-way Instruction cache\n",
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arm_picache_size / 1024,
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arm_picache_line_size, arm_picache_ways);
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aprint_normal_dev(dv, "%dKB/%dB %d-way %s Data cache\n",
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arm_pdcache_size / 1024,
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arm_pdcache_line_size, arm_pdcache_ways,
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wtnames[arm_pcache_type]);
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}
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if (arm_pcache_unified) {
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aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n",
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dv->dv_xname, arm_pdcache_size / 1024,
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arm_pdcache_line_size, arm_pdcache_ways,
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wtnames[arm_pcache_type]);
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} else {
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aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n",
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dv->dv_xname, arm_picache_size / 1024,
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arm_picache_line_size, arm_picache_ways);
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aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n",
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dv->dv_xname, arm_pdcache_size / 1024,
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arm_pdcache_line_size, arm_pdcache_ways,
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wtnames[arm_pcache_type]);
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}
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skip_pcache:
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switch (cpu_class) {
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#ifdef CPU_ARM2
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@ -646,19 +712,100 @@ identify_arm_cpu(device_t dv, struct cpu_info *ci)
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#endif
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break;
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default:
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if (cpu_classes[cpu_class].class_option == NULL)
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aprint_error("%s: %s does not fully support this CPU."
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"\n", dv->dv_xname, ostype);
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else {
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aprint_error("%s: This kernel does not fully support "
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"this CPU.\n", dv->dv_xname);
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aprint_normal("%s: Recompile with \"options %s\" to "
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"correct this.\n", dv->dv_xname,
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cpu_classes[cpu_class].class_option);
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if (cpu_classes[cpu_class].class_option == NULL) {
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aprint_error_dev(dv, "%s does not fully support this CPU.\n",
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ostype);
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} else {
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aprint_error_dev(dv, "This kernel does not fully support "
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"this CPU.\n");
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aprint_normal_dev(dv, "Recompile with \"options %s\" to "
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"correct this.\n", cpu_classes[cpu_class].class_option);
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}
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break;
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}
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}
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/* End of cpu.c */
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#ifdef CPU_CORTEX
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static void
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print_cortex_cache(device_t dv, u_int level, const char *desc)
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{
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uint32_t ccsidr = armreg_ccsidr_read();
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u_int linesize = 1 << ((ccsidr & 7) + 4);
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u_int nways = ((ccsidr >> 3) & 0x3ff) + 1;
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u_int nsets = ((ccsidr >> 13) & 0x7fff) + 1;
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u_int totalsize = linesize * nways * nsets;
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static const char * const wstrings[] = {
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"", " write-back", " write-through", ""
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};
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static const char * const astrings[] = {
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"",
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" with write allocate",
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" with read allocate",
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" with read and write allocate"
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};
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//aprint_debug_dev(dv, "ccsidr=%#x\n", ccsidr);
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u_int wtype = (ccsidr >> 30) & 3;
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u_int atype = (ccsidr >> 28) & 3;
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aprint_normal_dev(dv, "%uKB/%uB %u-way%s L%u %s cache%s\n",
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totalsize / 1024, linesize, nways, wstrings[wtype], level + 1,
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desc, astrings[atype]);
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}
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void
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identify_cortex_caches(device_t dv)
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{
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const uint32_t orig_csselr = armreg_csselr_read();
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uint32_t clidr = armreg_clidr_read();
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u_int level;
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//aprint_debug_dev(dv, "clidr=%011o\n", clidr);
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for (level = 0, clidr &= 077777777; clidr & 7; clidr >>= 3, level++) {
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if (clidr & 1) {
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armreg_csselr_write(2*level + 1);
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print_cortex_cache(dv, level, "Instruction");
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}
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if (clidr & 6) {
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armreg_csselr_write(2*level + 0);
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print_cortex_cache(dv, level,
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(clidr & 4) ? "Unified" : "Data");
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}
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}
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armreg_csselr_write(orig_csselr);
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}
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void
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identify_features(device_t dv)
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{
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uint32_t isar0 = armreg_isar0_read();
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uint32_t isar1 = armreg_isar1_read();
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uint32_t isar2 = armreg_isar2_read();
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uint32_t isar3 = armreg_isar3_read();
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uint32_t isar4 = armreg_isar4_read();
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uint32_t isar5 = armreg_isar5_read();
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uint32_t mmfr0 = armreg_mmfr0_read();
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uint32_t mmfr1 = armreg_mmfr1_read();
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uint32_t mmfr2 = armreg_mmfr2_read();
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uint32_t mmfr3 = armreg_mmfr3_read();
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uint32_t pfr0 = armreg_pfr0_read();
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uint32_t pfr1 = armreg_pfr1_read();
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aprint_normal_dev(dv,
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"isar: [0]=%#x [1]=%#x [2]=%#x [3]=%#x, [4]=%#x, [5]=%#x\n",
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isar0, isar1, isar2, isar3, isar4, isar5);
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aprint_normal_dev(dv,
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"mmfr: [0]=%#x [1]=%#x [2]=%#x [3]=%#x\n",
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mmfr0, mmfr1, mmfr2, mmfr3);
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aprint_normal_dev(dv,
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"pfr: [0]=%#x [1]=%#x\n",
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pfr0, pfr1);
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}
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#endif /* CPU_CORTEX */
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@ -1,4 +1,4 @@
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/* $NetBSD: armreg.h,v 1.59 2012/08/15 17:20:27 matt Exp $ */
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/* $NetBSD: armreg.h,v 1.60 2012/08/29 17:44:25 matt Exp $ */
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/*
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* Copyright (c) 1998, 2001 Ben Harris
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@ -212,8 +212,9 @@
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#define CPU_ID_CORTEXA9R4 0x413fc090
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#define CPU_ID_CORTEXA15R2 0x412fc0f0
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#define CPU_ID_CORTEXA15R3 0x413fc0f0
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#define CPU_ID_CORTEX_P(n) ((n & 0xff0fff00) == 0x410fc000)
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#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ffff0) == 0x410fc080)
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#define CPU_ID_CORTEX_P(n) ((n & 0xff0ff000) == 0x410fc000)
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#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080)
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#define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090)
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#define CPU_ID_SA110 0x4401a100
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#define CPU_ID_SA1100 0x4401a110
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#define CPU_ID_TI925T 0x54029250
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@ -343,6 +344,16 @@
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#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */
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#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */
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/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode2 1) */
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#define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Enable parity */
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#define CORTEXA9_AUXCTL_1WAY 0x00000100 /* Alloc in one way only */
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#define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache */
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#define CORTEXA9_AUXCTL_SMP 0x00000040 /* CPU is in SMP mode */
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#define CORTEXA9_AUXCTL_WRZERO 0x00000008 /* Write full line of zeroes */
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#define CORTEXA9_AUXCTL_L1PLD 0x00000004 /* L1 Dside prefetch */
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#define CORTEXA9_AUXCTL_L2PLD 0x00000002 /* L2 Dside prefetch */
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#define CORTEXA9_AUXCTL_FW 0x00000001 /* Forward Cache/TLB ops */
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/* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */
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#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
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#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
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@ -359,6 +370,16 @@
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#define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
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#define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */
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/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
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#define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */
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#define CORTEXA9_AUXCTL_L2_PLD 0x00000002 /* Prefetch hint enable */
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#define CORTEXA9_AUXCTL_L1_PLD 0x00000004 /* Data prefetch hint enable */
|
||||
#define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */
|
||||
#define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */
|
||||
#define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */
|
||||
#define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */
|
||||
#define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */
|
||||
|
||||
/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
|
||||
#define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */
|
||||
#define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */
|
||||
|
|
@ -509,4 +530,72 @@
|
|||
#define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */
|
||||
#define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */
|
||||
|
||||
#ifndef _LOCORE
|
||||
#define ARMREG_READ_INLINE(name, __insnstring) \
|
||||
static inline uint32_t armreg_##name##_read(void) \
|
||||
{ \
|
||||
uint32_t __rv; \
|
||||
__asm __volatile("mrc " __insnstring : "=r"(__rv)); \
|
||||
return __rv; \
|
||||
}
|
||||
|
||||
#define ARMREG_WRITE_INLINE(name, __insnstring) \
|
||||
static inline void armreg_##name##_write(uint32_t __val) \
|
||||
{ \
|
||||
__asm __volatile("mcr " __insnstring :: "r"(__val)); \
|
||||
}
|
||||
|
||||
/* c0 registers */
|
||||
ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */
|
||||
ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */
|
||||
ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */
|
||||
ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */
|
||||
ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */
|
||||
ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */
|
||||
ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */
|
||||
ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */
|
||||
ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */
|
||||
ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */
|
||||
ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */
|
||||
ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */
|
||||
ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */
|
||||
ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */
|
||||
ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */
|
||||
ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */
|
||||
ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */
|
||||
ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
|
||||
ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
|
||||
/* c2 registers */
|
||||
ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
|
||||
ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
|
||||
/* c9 registers */
|
||||
ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
|
||||
ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
|
||||
ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */
|
||||
ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */
|
||||
ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */
|
||||
ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */
|
||||
ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
|
||||
ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
|
||||
ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
|
||||
ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
|
||||
/* c13 registers */
|
||||
ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
|
||||
ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
|
||||
ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */
|
||||
/* c13 registers */
|
||||
ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
|
||||
ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
|
||||
ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
|
||||
ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
|
||||
|
||||
|
||||
#define MPIDR_31 0x80000000
|
||||
#define MPIDR_U 0x40000000 // 1 = Uniprocessor
|
||||
#define MPIDR_MT 0x01000000 // AFF0 for SMT
|
||||
#define MPIDR_AFF2 0x00ff0000
|
||||
#define MPIDR_AFF1 0x0000ff00
|
||||
#define MPIDR_AFF0 0x000000ff
|
||||
|
||||
#endif /* _LOCORE*/
|
||||
#endif /* _ARM_ARMREG_H */
|
||||
|
|
|
|||
|
|
@ -352,7 +352,7 @@ void cpu_proc_fork(struct proc *, struct proc *);
|
|||
*/
|
||||
|
||||
struct device;
|
||||
void cpu_attach(struct device *);
|
||||
void cpu_attach(device_t, cpuid_t);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: cpu_mainbus.c,v 1.11 2011/06/05 17:03:16 matt Exp $ */
|
||||
/* $NetBSD: cpu_mainbus.c,v 1.12 2012/08/29 17:44:25 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995 Mark Brinicombe.
|
||||
|
|
@ -42,7 +42,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: cpu_mainbus.c,v 1.11 2011/06/05 17:03:16 matt Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: cpu_mainbus.c,v 1.12 2012/08/29 17:44:25 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
|
@ -88,7 +88,7 @@ cpu_mainbus_match(device_t parent, cfdata_t cf, void *aux)
|
|||
static void
|
||||
cpu_mainbus_attach(device_t parent, device_t self, void *aux)
|
||||
{
|
||||
cpu_attach(self);
|
||||
cpu_attach(self, 0);
|
||||
}
|
||||
|
||||
CFATTACH_DECL_NEW(cpu_mainbus, 0,
|
||||
|
|
|
|||
Loading…
Reference in New Issue