mips struct cpu_info and related macroes.
The member was prepared for a hack in MD microtime(9) implementation
but it has been superseded by MI timecounter(9).
Fail sched_catchlwp() if mutex_tryenter() on the remote CPU's state fails.
Seems to work around the issue described in this PR.
XXX Stealing jobs from remote CPUs could probably be moved into the idle
loop, making the locking quite a bit simpler.
- Do timeslicing for SCHED_RR threads. At ~16Hz it's too slow but better
than nothing. XXX
- If a SCHED_OTHER thread has hogged the CPU for 1/8s without taking a
trip through mi_switch(), try to force a kernel preemption to give other
threads a chance.
than a zero-terminated list; this makes the code simpler and also
hopefully fixes the recent "childdet" botch, see PR kern/38528
-handle the root hub specially a bit earlier, this allows to kick out
the "submatch" functions completely which needed to second-guess
from the port number (where "0" meant root hub")
(we could handle the root hub specially even earlier, but as done
now big parts of the hub emulation code are exercised regularely,
this would bitrot otherwise)
physical drives belong to which logical drive, so all the physical drives
will show up for logical drive 0, and also appear for logical drives that
are rebuilding so that the rebuild state will show the physical drive
being rebuilt. Locking for the scratch buffer is currently missing - system
quickly quits responding when I try to lock the buffer with mutex_{enter,exit}().
AMD K8 and newer will trap when enabling the NX support outside PAE
paging mode. The AMD64 wake code was restoring the MSR EFER to switch to
Long Mode and naturally didn't have paging enabled at that point.
While this works fine with Intel CPUs, it resulted in an immediate
reboot with AMD processors.
Fixed by a joint brain storming session of jmcneill@, cegger@ and
myself, based on some input from the hardware developers. This fixes
PR 38587.
Also output any detected errata at verbose, rather than debug, level so
they can be seen with dmesg, and at least have a clue if a BIOS update
would fix the errata.
errata:
254: Internal Resource Livelock Involving Cached TLB Reload
261: Processor May Stall Entering Stop-Grant Due to Pending Data
Cache Scrub
298: L2 Eviction May Occur During Processor Operation To Set
Accessed or Dirty Bit
309: Processor Core May Execute Incorrect Instructions on
Concurrent L2 and Northbridge Response
ad