if CPU_SA110 is defined. Cache cleaning is different on the SA110 as
the cache is a write back virtual cache and is split for data and instruction.
Also the cache and tlb control instructions use different coprocessor #15
registers.
Removed suspect FPA probing code, instead use the ARM FPE to probe the FPA.
Neatened up the FPE attachment code.
Recognise StrongARM class of cpu.
Updated the fpa instruction bounce handler to expect a 4th argument
when called on an undefined trap to match recent changes made to
undefined handlers.
Add acknowledgement records to the buffer following origin or bounding
box changes.
Removed prototype for strncmp().
Added support for switch mouse reports between absolute and relative
positions.
This, in conjunction with the trap.c changes, solve the crashes when
referencing illegal addresses in the debugger. Thanks Jason for providing
the trigger and solution ;-)
- Re-write panictrap() so that faults generated by the debugger can be
handled by the debugger.
- Add a small bit of extra checking to the MMU_FAULT case, to make it more
robust against pieces of the proc-structure being NULL (Jason Thorpe)
- If p == NULL at the entry of trap(), assign proc0 to it. Fixes a *lot* of
NULL-pointer dereferences. (Gordon Ross)
immediately reasserted before we get a chance to process the interrupt,
we can inadvertantly get stuck with zs_tx_stopped set. Move the delta
detection to the hard zs interrupt handler; the softint handler
will notice that something has happened with CTS and restart the
transmitter if it's asserted.
brings us closer to basic operation.
- Verified/updated ROM vector entries for many systems, and new vector
table entries for LC 520, LC 575/577/578, and Quadra 950
- Implement a new machine class (MACH_CLASSQ2) for the LC 575 series
- Use the ptest040() helper function in get_physical().
Also, in straytrap(), only enter the debugger #ifdef DDB.
decent version numbers in them. This should really, really be in a
single file so in the future it only has to be changed in one place
for all distributions and documentation.
earlier stages of the NetBSD/arm32 development.
Added support for the architecture defined SWI's. Currently
The IMB and IMB-range architecture defined SWI's for the ARM810 are
currently recognised.
Various comments cleaned up.
