clean up some other stuff along the way, including:
- use m68k/cacheops.*, remove duplicates from cpu.h.
- centralize a few declarations in (all the copies of) cpu.h.
- define M68K_VAC on platforms which have a VAC.
- switch the sun platforms to the (now common) proc_trampoline().
- do the phys_map thang on the sun platforms too, no reason not to.
This merge changes the device switch tables from static array to
dynamically generated by config(8).
- All device switches is defined as a constant structure in device drivers.
- The new grammer ``device-major'' is introduced to ``files''.
device-major <prefix> char <num> [block <num>] [<rules>]
- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.
- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.
- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.
- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.
- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.
locations. If passed NULL, the old behaviour using bus_space_{read,write}_1()
is used. Otherwise, all access to the chip goes via the MD functions.
This is necessary for mvmeppc boards where the mk48txx NVRAM/RTC is not
directly addressable.
in preparation for future mvmeppc and mvme88k ports.
This needs a bit if tidying up to make it trully shareable, which will
happen as the new mvme ports are added.
for the i82596 PORT access interface, from the documentation
for that chip. These help clarify writes to the SYSBUS
part of the SCP, and PORT usage by i82596-aware drivers.
and attach it as `timekeeper0 at mainbus0'.
Use the MI mk48txx nvram/rtc access functions instead of home-grown
versions.
It should now be very easy to add a character device for the benefit
of userland access to NVRAM.
and attach it at mainbus since it depends both PCCChip2 and VMEChip2
(or the VMEChip2 interrupter) starting first.
We can finally enable, detect and log DRAM ECC errors.
(The PROM disabled ECC checks by default)
hardware-assisted soft interrupts on all boards.
(Note: VMEChip2-less 162/172 not yet tested)
This greatly simplifies the `rei' path and allows
interrupt nesting to be tracked somewhat more easily.
As a result we now have a working CLKF_INTR() macro
and can detect uvm_fault() being called from an interrupt
(although there may still be a very short race detecting
the latter; need to investigate further).
This is a completely rewritten scsipi_xfer execution engine, and the
associated changes to HBA drivers. Overview of changes & features:
- All xfers are queued in the mid-layer, rather than doing so in an
ad-hoc fashion in individual adapter drivers.
- Adapter/channel resource management in the mid-layer, avoids even trying
to start running an xfer if the adapter/channel doesn't have the resources.
- Better communication between the mid-layer and the adapters.
- Asynchronous event notification mechanism from adapter to mid-layer and
peripherals.
- Better peripheral queue management: freeze/thaw, sorted requeueing during
recovery, etc.
- Clean separation of peripherals, adapters, and adapter channels (no more
scsipi_link).
- Kernel thread for each scsipi_channel makes error recovery much easier
(no more dealing with interrupt context when recovering from an error).
- Mid-layer support for tagged queueing: commands can have the tag type
set explicitly, tag IDs are allocated in the mid-layer (thus eliminating
the need to use buggy tag ID allocation schemes in many adapter drivers).
- support for QUEUE FULL and CHECK CONDITION status in mid-layer; the command
will be requeued, or a REQUEST SENSE will be sent as appropriate.
Just before the merge syssrc has been tagged with thorpej_scsipi_beforemerge
This adds support for EtherExpress/16 cards with 16k of RAM, and in the
process adds general support for PIO mode on these cards. This entails
changing the way the i82586 driver handles bus barriers, since it doesn't
allow for strange cases like this.
This has been tested on the i386 port with the 'ix' driver in both
16KB (which was the source of the problem) and 32KB modes, as well
as with the 'ef' driver. I've tested it (briefly) with 'ei' on arm26
as well. In theory, drivers other than 'ix' should follow precisely the
same code paths as before.
