- IOMD specific interrupt handling. These files are mainly the old
arch/arm32/irq* files moved here and updated for new iomd device etc.
(revision history maintained).
These alternative macros have a workaround for the STM^ bug in revision < 3
StrongARM CPU's that causes incorrect register saving if a cache line fill
is in progress during the STM.
The irq delivery code has been rewritten. On entry to the irq vector the
processor is switched to SVC32 mode so all interrupt routines now run
in SVC32 mode rather than IRQ32 mode. This fixes lots of irq re-enabling
problems.
Interrupt latency times are now vastly improved for high priority interrupts.
Cleaned up calling ast() before returning to USR32 mode (don't need to
mess about with trapframe copying.
Cleaned up all the comments and sorted out their indentation.
Rewritten the soft interrupt delivery code.
Added generic ARM7500 support rather than just RC7500 support.
Added interrupt chaining.
Removed some dead debugging code.
Guarded several sanity checks with #ifdef DIAGNOSTIC
Make sure interrupts are disable while updating the IOMD interrupt
masks.