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b6c6870c6d
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47794 Commits

Author SHA1 Message Date
macallan
b6c6870c6d struct device * -> device_t 2008-05-16 02:41:50 +00:00
rjs
9a9e754190 Enable console on genfb(4). 2008-05-15 23:38:49 +00:00
rjs
89df53fa8e Enable DDB and INET6, remove use of md(4). 2008-05-15 23:36:47 +00:00
macallan
f147f68f57 listen to PMF volume control events 
With this volume vontrol via keyboard works on my iBook G4.
 2008-05-15 20:11:00 +00:00
macallan
7d61890be8 struct device -> device_t 2008-05-15 19:47:09 +00:00
nisimura
a63b802fd7 - cut half main.c and have brdsetup.c for cpu/board specifics. 
- introduce match() routine to stylise the way to pickup a PCI
  device driver.
- fix tlp.c error in the previous commit.
 2008-05-14 23:14:11 +00:00
tsutsui
b87210fa51 Normalize my licenses. 2008-05-14 13:29:27 +00:00
ad
bf1cf71fcd - cpu_attach: ensure that the boot processor is set up before trying to 
initialize APs. We need the lapic set up and the boot processor may
  not be attached first.

- mp_cpu_start: write back and invalidate the data cache before starting the
  init IPI sequence. If a buggy BIOS has left the AP with cache disabled,
  it might not be able to participate in the cache coherency protocol.
 2008-05-14 12:53:49 +00:00
he
30e1f3f935 Bump ramdisk size to compensate for recent bloat. 2008-05-14 08:08:31 +00:00
matt
082a2ff75b Back out SD/MMC inclusion which shouldn't have been comitted. 2008-05-14 01:58:29 +00:00
ad
5d1d928fe1 Be more conservative during AP startup. Don't let the AP access the lapic 
or do any setup until the boot processor has finished the init sequence,
and add a few more delays.
 2008-05-13 22:39:17 +00:00
ad
62118300c8 intr_string: don't bother printing the legacy irq number when using the 
ioapic. It's confusing.
 2008-05-13 20:19:26 +00:00
tsutsui
269bbddf81 Remove complete items (multi function PCI interrupts, zs on Qube2700). 2008-05-13 15:06:40 +00:00
joerg
816cef7d46 Restore the behaviour intended by rev 1.51 with the patch I actually 
send out for testing. The wrong version ended up in the commit.
Original description:
Don't use the legacy interrupt when deciding how to route IOAPIC pins.
On some modern systems not all devices have the PCI interrupt line
set, typically the cardbus bridge is affected and it would result in
different interrupt vectors used for the same IOAPIC pin.
To allow this, simplify the code by checking for an existing match first
and only allocate a new entry if that doesn't exist. For the IOAPIC case
don't bother with the reserveration on the primary CPU for ISA
interrupts, just use them.
 2008-05-13 14:29:17 +00:00
tsutsui
e04f8f6085 On netboot specify only FS_OPS(nfs) explicitly for file_system[] fs_ops. 
Trying block device fs_ops like ext2fs on netboot could be problematic
on some conditions since not all libsa functions handle errors properly.
 2008-05-13 14:26:20 +00:00
tsutsui
416b7a7683 Remove an unused extern declaration. 2008-05-13 14:20:58 +00:00
ad
6cd3bc13e5 PR port-amd64/38478 (panic on boot when attaching cpu17) 
Don't 'sti' before returning from an interrupt that is masked in software.
We could recurse and burn stack.
 2008-05-13 14:12:31 +00:00
ad
ef159c840a PR kern/35296 option PIC_DELAY not use 2008-05-13 13:43:47 +00:00
ad
5128f21c03 Back out 1.50 until the assumptions about NUM_LEGACY_IRQS are removed. 
Until then there are not enough free interrupt sources on UP systems.
(Sorry Joerg.)
 2008-05-13 12:14:06 +00:00
ad
25eae6f894 AMD and IDT/VIA strings were swapped. 2008-05-13 11:22:15 +00:00
ad
d3b40a28c7 - lapic_map: if we have an APIC MSR, ignore the supplied address and ask the 
hardware where it is mapped. At least one ACPI implementation seems to lie
  about the physical address of the lapic.

- lapic_initclocks: be paranoid and issue an EOI.
 2008-05-12 23:46:01 +00:00
ad
ce85d1b2a3 Some defs to describe the IA32_APIC_BASE MSR. 2008-05-12 18:36:20 +00:00
he
80dcfefbc7 Bump SYMTAB_SPACE so that it fits again. 2008-05-12 18:28:20 +00:00
tsutsui
6f98953d90 Remove one more dup line. I should have a cup of coffee before hasty commit.. 
XXX maybe it's better to sort by cai_desc to sync with the Intel docs.
 2008-05-12 16:41:15 +00:00
ad
a1ba1eadd5 - Make cpu_number() return MI index, otherwise the pmap cannot work on 
systems with lapic IDs > X86_MAXPROCS.
- Kill cpu_info[] array and use MI cpu_lookup_byindex().
 2008-05-12 14:41:07 +00:00
ad
02ce2ed48b Don't crash if more than 32 cpus. Hopefully the boot processor will be 
within the first 32 attached.
 2008-05-12 14:29:06 +00:00
ad
453d5d4dc1 - Complain if unable to reset the lapic ID. 
- Minor clean up.
 2008-05-12 14:19:33 +00:00
ad
094788ba6d cpu_hatch: hack around problem with multiple CPUs spinning in i8254_delay. 2008-05-12 11:58:10 +00:00
nisimura
ba7dbc0c82 CAL cache alignment band-aid for BMR register. 2008-05-12 11:56:15 +00:00
mlelstv
17740d28a4 add support for booting a kernel by tftp. Syntax is similar 
to other systems, e.g.: boot net tftp:netbsd
 2008-05-12 11:16:31 +00:00
nisimura
21ef04a5a6 sprincle volatile attribute for struct desc on memory to ease the 
target HW dependency on cache characteristic and load-store
serialization, and GCC compile time optimization strength.
 2008-05-12 09:58:36 +00:00
nisimura
3352c438fc Assign copyright notices. 2008-05-12 09:29:56 +00:00
simonb
ce7bd7383b Only need to add some of the new cache descriptors once(!). 2008-05-12 03:58:47 +00:00
he
d565d6ce16 Bump SYMTAB_SPACE so it fits again. 2008-05-11 23:34:40 +00:00
cegger
79c3bfd61b remove one indent level. No functional change. 2008-05-11 23:05:45 +00:00
yamt
bf5accf9f6 tprof_backend_estimate_freq: ci_tsc_freq -> ci_data.cpu_cc_freq 2008-05-11 22:51:02 +00:00
ad
31c3804afc - Decouple the APIC ID from cpu_info[]. 
- Probe TSC frequency on each AP when hatching.
 2008-05-11 22:26:59 +00:00
ad
0dc71691a0 Fix the qemu (?) problem. 2008-05-11 22:18:08 +00:00
ad
fff73dae94 splclock -> splhigh 2008-05-11 21:50:06 +00:00
ad
704c817f7a Use ci_cpumask. 2008-05-11 21:48:02 +00:00
cegger
c094da181a print L3 and TLB cache information for AMD Barcelona/Phenom 2008-05-11 21:19:17 +00:00
tsutsui
f256c15ff3 Update intel_cpuid_cache_info as per Intel's application note: 
"AP-485 Intel(R) Processor Identification and the CPUID Instruction"
http://www.intel.com/design/processor/applnots/241618.htm

XXX1: should sort by cai_index or cai_desc?
XXX2: should also check L3CACHE for coloring?
 2008-05-11 18:29:42 +00:00
tsutsui
ce7c3e5d1c Fix an indent. 2008-05-11 18:21:28 +00:00
ad
9188c0738a Wrap stuff in #ifdef _KERNEL 2008-05-11 16:57:43 +00:00
ad
a034c1c5e1 MP + apics are needed now so kill the #ifdefs 2008-05-11 16:26:56 +00:00
ad
bfff830416 Fix typo. 2008-05-11 16:25:46 +00:00
ad
b698c03c2c Don't reload LDTR unless a new value, which only happens for USER_LDT. 2008-05-11 16:23:05 +00:00
ad
5e605a64f7 Disable preemption across LDT mods. 2008-05-11 16:17:38 +00:00
ad
8250c8f097 Disable preemption over LDT modifications. 2008-05-11 16:13:34 +00:00
ad
3cd3c8ccbc Stop using APIC IDs to identify CPUs for software purposes. Allows for 
APIC IDs beyond 31, which has been possible for some time now.
 2008-05-11 15:59:50 +00:00