Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.
to avoid confusion.
Previous one (fdc->sc_addr + fddata) wasn't a right address for
the FDC's data register but one for the command register by accident,
but FDC ignores A0 address input (connected to A1 of x68k address bus)
during DMA xfer (i.e. when DACK is asserted) so it happened to work
as expected on the real X680x0 hardware, but caused trouble on emulators.
The inconsistency was found by Y.Sugahara during debugging XM6i emulator
(and it will be fixed in the next release).
FDC behavior during DMA is confirmed by uPD72068 hardware application note.
XXX: There is no proper MI API to specify DMA address for DMA controller
(like MC68450) to access devices mapped to memory space by bus_space(9).
their callback. That means the ucode buffer is released while still in use
and this causes a crash.
Quick fix: check if the ucode buffer has been freed and abort.
You may need to run 'cpuctl ucode' twice to apply it to all cpus.
Per discussion with rmind@ use low priority xcalls and splhigh.
excludes the 'jmp alltraps'.
Use the _NJ versions for trap entries with non-standard code.
Move all the KDTRACE_HOOKS code into a single block inside the
IDTVEC(trap03) code. This removes a mis-predicted from every
trap when KDTRACE_HOOKS are enabled.
Add a few blank lines, need some comments as well :-)
No functional changes intended.
Merge the XEN/non-XEN versions of INTRFASTEXIT and
INTR_RECURSE_HWFRAME by using extra defines.
Split INTRENTRY so that code can insert extra instructions
inside user/kernel conditional.
for ports which don't bother to have unnecessary bus_dma(9) implementation
to appease MI driver modules that require bus_dma_tag_t.
For amiga, move <m68k/bus_dma.h> inclusion from <machine/pci_machdep.h>
to <machine/bus.h> since amiga will want actual bus_dma(9) in future
for PCI devices.
Fixes builds on sys/modules/if_axe etc on ancient ports.
"Sounds good" from martin@ on port-m68k@.
Use this opportunity to skip calculating the VA of the page. Let the CPU
deal with the invalidation itself through invlpg + destination address to
avoid converting between canonical/non canonical forms.
the TLB and the CPU will not notice the access right change.
This results in write protection faults in supervisor mode when patching
kernel code through ddb(4) (originally mapped as read only).
Bug reported by David Laight on port-amd64@ (thanks!), patch and test by
me.
i386 is unaffected as PG_LGFRAME does not mask the sign bits. For the
sake of correctness, use VA_SIGN_NEG(...) anyway.
XXX this is the patch that will be pulled-up to -5 and -6.
calls as these operations are synchronously flushed under Xen; they should
not be cached.
XXX the code can be shared between i386 and amd64, but I will merge
them once I figure out why db_write_text() can cause page faults for
certain CPUs in long mode (code looks correct, but single stepping or
adding debug printf's makes the bug magically disappear... sigh)
Bug reported by David Laight on port-amd64@ when attempting to set
breakpoints through ddb(4).
on machines with extended high memories:
- dev/fd.c:
- add missing bus_dmamap_sync(9) POSTREAD/POSTWRITE ops
- x68k/machdep.c:
- update avail_end variable (which is used to check DMA'able memory range
in intio.c) properly per probed extended memory regions
The problem was found during debugging XM6i's FDC emulation by
Y.Sugahara, isaki@, and me.
Should be pulled up to netbsd-6.
- CR4_VMXE: VMX operations, used for hardware virtualization.
- CR4_SMXE: SMX operations, used for safer Mode Extensions (ground for
Intel's TXT - Trusted Execution Technology - platform).
- CR4_FSGSBASE: enable *FSBASE and *GSBASE instructions, for R/W access
to FS/GS segment base addresses.
- CR4_PCIDE: enable Process Context IDentifiers (other architectures may call
these "address space identifiers").
- CR4_OSXSAVE: enable xsave and xrestore instructions
- CR4_SMEP: Supervisor Mode Execution Prevention. Allows enforcing --x rights
from cpl 0.
From Intel® 64 and IA-32 Architectures Software Developer’s Manual,
March 2012.
Align declarations.
CPUID_* bits for these features follow.
isaki