Rename register values. No functional change - same code before and after.
Existing names are prefixed with PL01X_ where they're common between the PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're found only on the respective chips.
This commit is contained in:
skrll
parent
59e244130f
commit
b9703c3d18
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@ -1,4 +1,4 @@
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/* $NetBSD: plcom.c,v 1.34 2012/04/06 01:47:16 bsh Exp $ */
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/* $NetBSD: plcom.c,v 1.35 2012/05/14 19:40:06 skrll Exp $ */
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/*-
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* Copyright (c) 2001 ARM Ltd
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@ -94,7 +94,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: plcom.c,v 1.34 2012/04/06 01:47:16 bsh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: plcom.c,v 1.35 2012/05/14 19:40:06 skrll Exp $");
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#include "opt_plcom.h"
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#include "opt_ddb.h"
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@ -289,17 +289,17 @@ plcomstatus(struct plcom_softc *sc, const char *str)
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printf("%s: %s %sclocal %sdcd %sts_carr_on %sdtr %stx_stopped\n",
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sc->sc_dev.dv_xname, str,
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ISSET(tp->t_cflag, CLOCAL) ? "+" : "-",
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ISSET(sc->sc_msr, MSR_DCD) ? "+" : "-",
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ISSET(sc->sc_msr, PL01X_MSR_DCD) ? "+" : "-",
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ISSET(tp->t_state, TS_CARR_ON) ? "+" : "-",
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ISSET(sc->sc_mcr, MCR_DTR) ? "+" : "-",
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ISSET(sc->sc_mcr, PL01X_MCR_DTR) ? "+" : "-",
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sc->sc_tx_stopped ? "+" : "-");
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printf("%s: %s %scrtscts %scts %sts_ttstop %srts %xrx_flags\n",
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sc->sc_dev.dv_xname, str,
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ISSET(tp->t_cflag, CRTSCTS) ? "+" : "-",
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ISSET(sc->sc_msr, MSR_CTS) ? "+" : "-",
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ISSET(sc->sc_msr, PL01X_MSR_CTS) ? "+" : "-",
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ISSET(tp->t_state, TS_TTSTOP) ? "+" : "-",
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ISSET(sc->sc_mcr, MCR_RTS) ? "+" : "-",
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ISSET(sc->sc_mcr, PL01X_MCR_RTS) ? "+" : "-",
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sc->sc_rx_flags);
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}
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#endif
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@ -313,19 +313,19 @@ plcomprobe1(bus_space_tag_t iot, bus_space_handle_t ioh)
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/* Disable the UART. */
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bus_space_write_1(iot, ioh, plcom_cr, 0);
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/* Make sure the FIFO is off. */
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bus_space_write_1(iot, ioh, plcom_lcr, LCR_8BITS);
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bus_space_write_1(iot, ioh, plcom_lcr, PL01X_LCR_8BITS);
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/* Disable interrupts. */
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bus_space_write_1(iot, ioh, plcom_iir, 0);
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/* Make sure we swallow anything in the receiving register. */
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data = bus_space_read_1(iot, ioh, plcom_dr);
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if (bus_space_read_1(iot, ioh, plcom_lcr) != LCR_8BITS)
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if (bus_space_read_1(iot, ioh, plcom_lcr) != PL01X_LCR_8BITS)
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return 0;
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data = bus_space_read_1(iot, ioh, plcom_fr) & (FR_RXFF | FR_RXFE);
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data = bus_space_read_1(iot, ioh, plcom_fr) & (PL01X_FR_RXFF | PL01X_FR_RXFE);
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if (data != FR_RXFE)
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if (data != PL01X_FR_RXFE)
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return 0;
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return 1;
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@ -339,9 +339,9 @@ plcom_enable_debugport(struct plcom_softc *sc)
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/* Turn on line break interrupt, set carrier. */
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s = splserial();
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PLCOM_LOCK(sc);
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sc->sc_cr = CR_RIE | CR_RTIE | CR_UARTEN;
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sc->sc_cr = PL010_CR_RIE | PL010_CR_RTIE | PL01X_CR_UARTEN;
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, plcom_cr, sc->sc_cr);
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SET(sc->sc_mcr, MCR_DTR | MCR_RTS);
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SET(sc->sc_mcr, PL01X_MCR_DTR | PL01X_MCR_RTS);
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/* XXX device_unit() abuse */
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sc->sc_set_mcr(sc->sc_set_mcr_arg, device_unit(&sc->sc_dev),
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sc->sc_mcr);
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@ -375,7 +375,7 @@ plcom_attach_subr(struct plcom_softc *sc)
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SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
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/* Must re-enable the console immediately, or we will
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hang when trying to print. */
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sc->sc_cr = CR_UARTEN;
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sc->sc_cr = PL01X_CR_UARTEN;
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}
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bus_space_write_1(iot, ioh, plcom_cr, sc->sc_cr);
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@ -562,7 +562,7 @@ plcom_shutdown(struct plcom_softc *sc)
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/* Turn off interrupts. */
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if (ISSET(sc->sc_hwflags, PLCOM_HW_CONSOLE))
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/* interrupt on break */
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sc->sc_cr = CR_RIE | CR_RTIE | CR_UARTEN;
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sc->sc_cr = PL010_CR_RIE | PL010_CR_RTIE | PL01X_CR_UARTEN;
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else
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sc->sc_cr = 0;
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, plcom_cr, sc->sc_cr);
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@ -636,7 +636,7 @@ plcomopen(dev_t dev, int flag, int mode, struct lwp *l)
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/* Turn on interrupts. */
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/* IER_ERXRDY | IER_ERLS | IER_EMSC; */
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sc->sc_cr = CR_RIE | CR_RTIE | CR_MSIE | CR_UARTEN;
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sc->sc_cr = PL010_CR_RIE | PL010_CR_RTIE | PL010_CR_MSIE | PL01X_CR_UARTEN;
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, plcom_cr, sc->sc_cr);
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/* Fetch the current modem control status, needed later. */
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@ -919,20 +919,20 @@ plcomioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
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break;
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case PPS_CAPTUREASSERT:
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sc->sc_ppsmask = MSR_DCD;
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sc->sc_ppsassert = MSR_DCD;
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sc->sc_ppsmask = PL01X_MSR_DCD;
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sc->sc_ppsassert = PL01X_MSR_DCD;
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sc->sc_ppsclear = -1;
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break;
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case PPS_CAPTURECLEAR:
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sc->sc_ppsmask = MSR_DCD;
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sc->sc_ppsmask = PL01X_MSR_DCD;
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sc->sc_ppsassert = -1;
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sc->sc_ppsclear = 0;
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break;
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case PPS_CAPTUREBOTH:
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sc->sc_ppsmask = MSR_DCD;
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sc->sc_ppsassert = MSR_DCD;
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sc->sc_ppsmask = PL01X_MSR_DCD;
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sc->sc_ppsassert = PL01X_MSR_DCD;
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sc->sc_ppsclear = 0;
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break;
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@ -964,9 +964,9 @@ plcomioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
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* The old API has no way to specify PPS polarity.
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*/
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mutex_spin_enter(&timecounter_lock);
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sc->sc_ppsmask = MSR_DCD;
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sc->sc_ppsmask = PL01X_MSR_DCD;
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#ifndef PPS_TRAILING_EDGE
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sc->sc_ppsassert = MSR_DCD;
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sc->sc_ppsassert = PL01X_MSR_DCD;
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sc->sc_ppsclear = -1;
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TIMESPEC_TO_TIMEVAL((struct timeval *)data,
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&sc->ppsinfo.assert_timestamp);
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@ -1010,9 +1010,9 @@ plcom_break(struct plcom_softc *sc, int onoff)
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{
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if (onoff)
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SET(sc->sc_lcr, LCR_BRK);
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SET(sc->sc_lcr, PL01X_LCR_BRK);
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else
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CLR(sc->sc_lcr, LCR_BRK);
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CLR(sc->sc_lcr, PL01X_LCR_BRK);
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if (!sc->sc_heldchange) {
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if (sc->sc_tx_busy) {
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@ -1053,9 +1053,9 @@ tiocm_to_plcom(struct plcom_softc *sc, u_long how, int ttybits)
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plcombits = 0;
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if (ISSET(ttybits, TIOCM_DTR))
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SET(plcombits, MCR_DTR);
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SET(plcombits, PL01X_MCR_DTR);
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if (ISSET(ttybits, TIOCM_RTS))
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SET(plcombits, MCR_RTS);
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SET(plcombits, PL01X_MCR_RTS);
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switch (how) {
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case TIOCMBIC:
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@ -1067,7 +1067,7 @@ tiocm_to_plcom(struct plcom_softc *sc, u_long how, int ttybits)
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break;
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case TIOCMSET:
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CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
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CLR(sc->sc_mcr, PL01X_MCR_DTR | PL01X_MCR_RTS);
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SET(sc->sc_mcr, plcombits);
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break;
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}
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@ -1089,17 +1089,17 @@ plcom_to_tiocm(struct plcom_softc *sc)
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int ttybits = 0;
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plcombits = sc->sc_mcr;
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if (ISSET(plcombits, MCR_DTR))
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if (ISSET(plcombits, PL01X_MCR_DTR))
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SET(ttybits, TIOCM_DTR);
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if (ISSET(plcombits, MCR_RTS))
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if (ISSET(plcombits, PL01X_MCR_RTS))
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SET(ttybits, TIOCM_RTS);
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plcombits = sc->sc_msr;
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if (ISSET(plcombits, MSR_DCD))
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if (ISSET(plcombits, PL01X_MSR_DCD))
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SET(ttybits, TIOCM_CD);
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if (ISSET(plcombits, MSR_CTS))
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if (ISSET(plcombits, PL01X_MSR_CTS))
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SET(ttybits, TIOCM_CTS);
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if (ISSET(plcombits, MSR_DSR))
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if (ISSET(plcombits, PL01X_MSR_DSR))
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SET(ttybits, TIOCM_DSR);
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if (sc->sc_cr != 0)
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@ -1115,25 +1115,25 @@ cflag2lcr(tcflag_t cflag)
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switch (ISSET(cflag, CSIZE)) {
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case CS5:
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SET(lcr, LCR_5BITS);
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SET(lcr, PL01X_LCR_5BITS);
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break;
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case CS6:
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SET(lcr, LCR_6BITS);
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SET(lcr, PL01X_LCR_6BITS);
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break;
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case CS7:
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SET(lcr, LCR_7BITS);
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SET(lcr, PL01X_LCR_7BITS);
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break;
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case CS8:
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SET(lcr, LCR_8BITS);
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SET(lcr, PL01X_LCR_8BITS);
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break;
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}
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if (ISSET(cflag, PARENB)) {
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SET(lcr, LCR_PEN);
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SET(lcr, PL01X_LCR_PEN);
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if (!ISSET(cflag, PARODD))
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SET(lcr, LCR_EPS);
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SET(lcr, PL01X_LCR_EPS);
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}
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if (ISSET(cflag, CSTOPB))
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SET(lcr, LCR_STP2);
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SET(lcr, PL01X_LCR_STP2);
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return lcr;
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}
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@ -1177,7 +1177,7 @@ plcomparam(struct tty *tp, struct termios *t)
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tp->t_cflag == t->c_cflag)
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return 0;
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lcr = ISSET(sc->sc_lcr, LCR_BRK) | cflag2lcr(t->c_cflag);
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lcr = ISSET(sc->sc_lcr, PL01X_LCR_BRK) | cflag2lcr(t->c_cflag);
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s = splserial();
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PLCOM_LOCK(sc);
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@ -1193,7 +1193,7 @@ plcomparam(struct tty *tp, struct termios *t)
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sc->sc_fifo = 0;
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if (sc->sc_fifo)
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SET(sc->sc_lcr, LCR_FEN);
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SET(sc->sc_lcr, PL01X_LCR_FEN);
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/*
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* If we're not in a mode that assumes a connection is present, then
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@ -1202,36 +1202,36 @@ plcomparam(struct tty *tp, struct termios *t)
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if (ISSET(t->c_cflag, CLOCAL | MDMBUF))
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sc->sc_msr_dcd = 0;
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else
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sc->sc_msr_dcd = MSR_DCD;
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sc->sc_msr_dcd = PL01X_MSR_DCD;
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/*
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* Set the flow control pins depending on the current flow control
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* mode.
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*/
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if (ISSET(t->c_cflag, CRTSCTS)) {
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sc->sc_mcr_dtr = MCR_DTR;
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sc->sc_mcr_rts = MCR_RTS;
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sc->sc_msr_cts = MSR_CTS;
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sc->sc_mcr_dtr = PL01X_MCR_DTR;
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sc->sc_mcr_rts = PL01X_MCR_RTS;
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sc->sc_msr_cts = PL01X_MSR_CTS;
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} else if (ISSET(t->c_cflag, MDMBUF)) {
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/*
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* For DTR/DCD flow control, make sure we don't toggle DTR for
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* carrier detection.
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*/
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sc->sc_mcr_dtr = 0;
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sc->sc_mcr_rts = MCR_DTR;
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sc->sc_msr_cts = MSR_DCD;
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sc->sc_mcr_rts = PL01X_MCR_DTR;
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sc->sc_msr_cts = PL01X_MSR_DCD;
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} else {
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/*
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* If no flow control, then always set RTS. This will make
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* the other side happy if it mistakenly thinks we're doing
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* RTS/CTS flow control.
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*/
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sc->sc_mcr_dtr = MCR_DTR | MCR_RTS;
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sc->sc_mcr_dtr = PL01X_MCR_DTR | PL01X_MCR_RTS;
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sc->sc_mcr_rts = 0;
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sc->sc_msr_cts = 0;
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if (ISSET(sc->sc_mcr, MCR_DTR))
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SET(sc->sc_mcr, MCR_RTS);
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if (ISSET(sc->sc_mcr, PL01X_MCR_DTR))
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SET(sc->sc_mcr, PL01X_MCR_RTS);
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else
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CLR(sc->sc_mcr, MCR_RTS);
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CLR(sc->sc_mcr, PL01X_MCR_RTS);
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}
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sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd;
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@ -1284,7 +1284,7 @@ plcomparam(struct tty *tp, struct termios *t)
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* CLOCAL or MDMBUF. We don't hang up here; we only do that by
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* explicit request.
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*/
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(void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD));
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(void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, PL01X_MSR_DCD));
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#ifdef PLCOM_DEBUG
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if (plcom_debug)
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@ -1316,7 +1316,7 @@ plcom_iflush(struct plcom_softc *sc)
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#endif
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timo = 50000;
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/* flush any pending I/O */
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while (! ISSET(bus_space_read_1(iot, ioh, plcom_fr), FR_RXFE)
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while (! ISSET(bus_space_read_1(iot, ioh, plcom_fr), PL01X_FR_RXFE)
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&& --timo)
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#ifdef DIAGNOSTIC
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reg =
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@ -1451,8 +1451,8 @@ plcomstart(struct tty *tp)
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sc->sc_tx_busy = 1;
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/* Enable transmit completion interrupts if necessary. */
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if (!ISSET(sc->sc_cr, CR_TIE)) {
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SET(sc->sc_cr, CR_TIE);
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if (!ISSET(sc->sc_cr, PL010_CR_TIE)) {
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SET(sc->sc_cr, PL010_CR_TIE);
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bus_space_write_1(iot, ioh, plcom_cr, sc->sc_cr);
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}
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@ -1543,16 +1543,16 @@ plcom_rxsoft(struct plcom_softc *sc, struct tty *tp)
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while (cc) {
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code = get[0];
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rsr = get[1];
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if (ISSET(rsr, RSR_OE | RSR_BE | RSR_FE | RSR_PE)) {
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if (ISSET(rsr, RSR_OE)) {
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if (ISSET(rsr, PL01X_RSR_ERROR)) {
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if (ISSET(rsr, PL01X_RSR_OE)) {
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sc->sc_overflows++;
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if (sc->sc_errors++ == 0)
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callout_reset(&sc->sc_diag_callout,
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60 * hz, plcomdiag, sc);
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}
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if (ISSET(rsr, RSR_BE | RSR_FE))
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if (ISSET(rsr, PL01X_RSR_BE | PL01X_RSR_FE))
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SET(code, TTY_FE);
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if (ISSET(rsr, RSR_PE))
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if (ISSET(rsr, PL01X_RSR_PE))
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SET(code, TTY_PE);
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}
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if ((*rint)(code, tp) == -1) {
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@ -1599,7 +1599,7 @@ plcom_rxsoft(struct plcom_softc *sc, struct tty *tp)
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if (cc >= sc->sc_r_lowat) {
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if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
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CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
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SET(sc->sc_cr, CR_RIE | CR_RTIE);
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SET(sc->sc_cr, PL010_CR_RIE | PL010_CR_RTIE);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh, plcom_cr, sc->sc_cr);
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}
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if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
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@ -1642,7 +1642,7 @@ plcom_stsoft(struct plcom_softc *sc, struct tty *tp)
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/*
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* Inform the tty layer that carrier detect changed.
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*/
|
||||
(void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD));
|
||||
(void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, PL01X_MSR_DCD));
|
||||
}
|
||||
|
||||
if (ISSET(delta, sc->sc_msr_cts)) {
|
||||
|
|
@ -1703,7 +1703,7 @@ plcomintr(void *arg)
|
|||
|
||||
PLCOM_LOCK(sc);
|
||||
iir = bus_space_read_1(iot, ioh, plcom_iir);
|
||||
if (! ISSET(iir, IIR_IMASK)) {
|
||||
if (! ISSET(iir, PL010_IIR_IMASK)) {
|
||||
PLCOM_UNLOCK(sc);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1717,7 +1717,7 @@ plcomintr(void *arg)
|
|||
|
||||
fr = bus_space_read_1(iot, ioh, plcom_fr);
|
||||
|
||||
if (!ISSET(fr, FR_RXFE) &&
|
||||
if (!ISSET(fr, PL01X_FR_RXFE) &&
|
||||
!ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
|
||||
while (cc > 0) {
|
||||
int cn_trapped = 0;
|
||||
|
|
@ -1725,11 +1725,10 @@ plcomintr(void *arg)
|
|||
plcom_dr);
|
||||
rsr = bus_space_read_1(iot, ioh, plcom_rsr);
|
||||
/* Clear any error status. */
|
||||
if (ISSET(rsr,
|
||||
(RSR_BE | RSR_OE | RSR_PE | RSR_FE)))
|
||||
if (ISSET(rsr, PL01X_RSR_ERROR))
|
||||
bus_space_write_1(iot, ioh, plcom_ecr,
|
||||
0);
|
||||
if (ISSET(rsr, RSR_BE)) {
|
||||
if (ISSET(rsr, PL01X_RSR_BE)) {
|
||||
cn_trapped = 0;
|
||||
cn_check_magic(sc->sc_tty->t_dev,
|
||||
CNC_BREAK, plcom_cnm_state);
|
||||
|
|
@ -1751,7 +1750,7 @@ plcomintr(void *arg)
|
|||
if (cn_trapped) {
|
||||
fr = bus_space_read_1(iot, ioh,
|
||||
plcom_fr);
|
||||
if (ISSET(fr, FR_RXFE))
|
||||
if (ISSET(fr, PL01X_FR_RXFE))
|
||||
break;
|
||||
|
||||
continue;
|
||||
|
|
@ -1762,7 +1761,7 @@ plcomintr(void *arg)
|
|||
cc--;
|
||||
|
||||
fr = bus_space_read_1(iot, ioh, plcom_fr);
|
||||
if (ISSET(fr, FR_RXFE))
|
||||
if (ISSET(fr, PL01X_FR_RXFE))
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1793,12 +1792,12 @@ plcomintr(void *arg)
|
|||
*/
|
||||
if (!cc) {
|
||||
SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
|
||||
CLR(sc->sc_cr, CR_RIE | CR_RTIE);
|
||||
CLR(sc->sc_cr, PL010_CR_RIE | PL010_CR_RTIE);
|
||||
bus_space_write_1(iot, ioh, plcom_cr,
|
||||
sc->sc_cr);
|
||||
}
|
||||
} else {
|
||||
if (ISSET(iir, IIR_RIS)) {
|
||||
if (ISSET(iir, PL010_IIR_RIS)) {
|
||||
bus_space_write_1(iot, ioh, plcom_cr, 0);
|
||||
delay(10);
|
||||
bus_space_write_1(iot, ioh, plcom_cr,
|
||||
|
|
@ -1811,7 +1810,7 @@ plcomintr(void *arg)
|
|||
delta = msr ^ sc->sc_msr;
|
||||
sc->sc_msr = msr;
|
||||
/* Clear any pending modem status interrupt. */
|
||||
if (iir & IIR_MIS)
|
||||
if (iir & PL010_IIR_MIS)
|
||||
bus_space_write_1(iot, ioh, plcom_icr, 0);
|
||||
/*
|
||||
* Pulse-per-second (PSS) signals on edge of DCD?
|
||||
|
|
@ -1886,7 +1885,7 @@ plcomintr(void *arg)
|
|||
* can be * transmitted as well. Schedule tx done
|
||||
* event if no data left * and tty was marked busy.
|
||||
*/
|
||||
if (ISSET(iir, IIR_TIS)) {
|
||||
if (ISSET(iir, PL010_IIR_TIS)) {
|
||||
/*
|
||||
* If we've delayed a parameter change, do it
|
||||
* now, and restart * output.
|
||||
|
|
@ -1917,8 +1916,8 @@ plcomintr(void *arg)
|
|||
* Disable transmit plcompletion
|
||||
* interrupts if necessary.
|
||||
*/
|
||||
if (ISSET(sc->sc_cr, CR_TIE)) {
|
||||
CLR(sc->sc_cr, CR_TIE);
|
||||
if (ISSET(sc->sc_cr, PL010_CR_TIE)) {
|
||||
CLR(sc->sc_cr, PL010_CR_TIE);
|
||||
bus_space_write_1(iot, ioh, plcom_cr,
|
||||
sc->sc_cr);
|
||||
}
|
||||
|
|
@ -1929,7 +1928,7 @@ plcomintr(void *arg)
|
|||
}
|
||||
}
|
||||
} while (ISSET((iir = bus_space_read_1(iot, ioh, plcom_iir)),
|
||||
IIR_IMASK));
|
||||
PL010_IIR_IMASK));
|
||||
|
||||
PLCOM_UNLOCK(sc);
|
||||
|
||||
|
|
@ -1976,7 +1975,7 @@ plcom_common_getc(dev_t dev, bus_space_tag_t iot, bus_space_handle_t ioh)
|
|||
}
|
||||
|
||||
/* block until a character becomes available */
|
||||
while (ISSET(stat = bus_space_read_1(iot, ioh, plcom_fr), FR_RXFE))
|
||||
while (ISSET(stat = bus_space_read_1(iot, ioh, plcom_fr), PL01X_FR_RXFE))
|
||||
;
|
||||
|
||||
c = bus_space_read_1(iot, ioh, plcom_dr);
|
||||
|
|
@ -2002,7 +2001,7 @@ plcom_common_putc(dev_t dev, bus_space_tag_t iot, bus_space_handle_t ioh,
|
|||
|
||||
int cin, stat;
|
||||
if (plcom_readaheadcount < MAX_READAHEAD
|
||||
&& !ISSET(stat = bus_space_read_1(iot, ioh, plcom_fr), FR_RXFE)) {
|
||||
&& !ISSET(stat = bus_space_read_1(iot, ioh, plcom_fr), PL01X_FR_RXFE)) {
|
||||
int cn_trapped = 0;
|
||||
cin = bus_space_read_1(iot, ioh, plcom_dr);
|
||||
stat = bus_space_read_1(iot, ioh, plcom_iir);
|
||||
|
|
@ -2012,7 +2011,7 @@ plcom_common_putc(dev_t dev, bus_space_tag_t iot, bus_space_handle_t ioh,
|
|||
|
||||
/* wait for any pending transmission to finish */
|
||||
timo = 150000;
|
||||
while (!ISSET(bus_space_read_1(iot, ioh, plcom_fr), FR_TXFE) && --timo)
|
||||
while (!ISSET(bus_space_read_1(iot, ioh, plcom_fr), PL01X_FR_TXFE) && --timo)
|
||||
continue;
|
||||
|
||||
bus_space_write_1(iot, ioh, plcom_dr, c);
|
||||
|
|
@ -2020,7 +2019,7 @@ plcom_common_putc(dev_t dev, bus_space_tag_t iot, bus_space_handle_t ioh,
|
|||
|
||||
/* wait for this transmission to complete */
|
||||
timo = 1500000;
|
||||
while (!ISSET(bus_space_read_1(iot, ioh, plcom_fr), FR_TXFE) && --timo)
|
||||
while (!ISSET(bus_space_read_1(iot, ioh, plcom_fr), PL01X_FR_TXFE) && --timo)
|
||||
continue;
|
||||
|
||||
splx(s);
|
||||
|
|
@ -2042,15 +2041,15 @@ plcominit(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency,
|
|||
bus_space_write_1(iot, ioh, plcom_cr, 0);
|
||||
bus_space_write_1(iot, ioh, plcom_dlbl, rate);
|
||||
bus_space_write_1(iot, ioh, plcom_dlbh, rate >> 8);
|
||||
bus_space_write_1(iot, ioh, plcom_lcr, cflag2lcr(cflag) | LCR_FEN);
|
||||
bus_space_write_1(iot, ioh, plcom_cr, CR_UARTEN);
|
||||
bus_space_write_1(iot, ioh, plcom_lcr, cflag2lcr(cflag) | PL01X_LCR_FEN);
|
||||
bus_space_write_1(iot, ioh, plcom_cr, PL01X_CR_UARTEN);
|
||||
|
||||
#if 0
|
||||
/* Ought to do something like this, but we have no sc to
|
||||
dereference. */
|
||||
/* XXX device_unit() abuse */
|
||||
sc->sc_set_mcr(sc->sc_set_mcr_arg, device_unit(&sc->sc_dev),
|
||||
MCR_DTR | MCR_RTS);
|
||||
PL01X_MCR_DTR | PL01X_MCR_RTS);
|
||||
#endif
|
||||
|
||||
*iohp = ioh;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: plcomreg.h,v 1.2 2012/04/06 01:35:58 bsh Exp $ */
|
||||
/* $NetBSD: plcomreg.h,v 1.3 2012/05/14 19:40:06 skrll Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2001 ARM Ltd
|
||||
|
|
@ -34,63 +34,91 @@
|
|||
#define PLCOM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */
|
||||
|
||||
/* control register */
|
||||
#define CR_LBE 0x80 /* Loopback enable */
|
||||
#define CR_RTIE 0x40 /* Receive timeout interrupt enable */
|
||||
#define CR_TIE 0x20 /* Transmit interrupt enable */
|
||||
#define CR_RIE 0x10 /* Receive interrrupt enable */
|
||||
#define CR_MSIE 0x08 /* Modem status interrupt enable */
|
||||
#define CR_SIRLP 0x04 /* IrDA SIR Low power mode */
|
||||
#define CR_SIREN 0x02 /* SIR Enable */
|
||||
#define CR_UARTEN 0x01 /* Uart enable */
|
||||
#define PL011_CR_CTSEN 0x8000 /* CTS HW flow control enable */
|
||||
#define PL011_CR_RTSEN 0x4000 /* RTS HW flow control enable */
|
||||
#define PL011_CR_OUT2 0x2000 /* Complement of UART Out2 MSR */
|
||||
#define PL011_CR_OUT1 0x1000 /* Complement of UART Out1 MSR */
|
||||
#define PL011_CR_RTS 0x0800 /* Request to send */
|
||||
#define PL011_CR_DTR 0x0400 /* Data transmit Ready */
|
||||
#define PL011_CR_RXE 0x0200 /* Receive enable */
|
||||
#define PL011_CR_TXE 0x0100 /* Transmit enable */
|
||||
#define PL01X_CR_LBE 0x0080 /* Loopback enable */
|
||||
#define PL010_CR_RTIE 0x0040 /* Receive timeout interrupt enable */
|
||||
#define PL010_CR_TIE 0x0020 /* Transmit interrupt enable */
|
||||
#define PL010_CR_RIE 0x0010 /* Receive interrrupt enable */
|
||||
#define PL010_CR_MSIE 0x0008 /* Modem status interrupt enable */
|
||||
#define PL01X_CR_SIRLP 0x0004 /* IrDA SIR Low power mode */
|
||||
#define PL01X_CR_SIREN 0x0002 /* SIR Enable */
|
||||
#define PL01X_CR_UARTEN 0x0001 /* Uart enable */
|
||||
|
||||
/* interrupt identification register */
|
||||
#define IIR_IMASK 0x0f
|
||||
#define IIR_RTIS 0x08
|
||||
#define IIR_TIS 0x04
|
||||
#define IIR_RIS 0x02
|
||||
#define IIR_MIS 0x01
|
||||
#define PL010_IIR_IMASK 0x0f
|
||||
#define PL010_IIR_RTIS 0x08
|
||||
#define PL010_IIR_TIS 0x04
|
||||
#define PL010_IIR_RIS 0x02
|
||||
#define PL010_IIR_MIS 0x01
|
||||
|
||||
/* line control register */
|
||||
#define LCR_WLEN 0x60 /* Mask of size bits */
|
||||
#define LCR_8BITS 0x60 /* 8 bits per serial word */
|
||||
#define LCR_7BITS 0x40 /* 7 bits */
|
||||
#define LCR_6BITS 0x20 /* 6 bits */
|
||||
#define LCR_5BITS 0x00 /* 5 bits */
|
||||
#define LCR_FEN 0x10 /* FIFO enable */
|
||||
#define LCR_STP2 0x08 /* 2 stop bits per serial word */
|
||||
#define LCR_EPS 0x04 /* Even parity select */
|
||||
#define LCR_PEN 0x02 /* Parity enable */
|
||||
#define LCR_PEVEN (LCR_PEN | LCR_EPS)
|
||||
#define LCR_PODD LCR_PEN
|
||||
#define LCR_PNONE 0x00 /* No parity */
|
||||
#define LCR_BRK 0x01 /* Break Control */
|
||||
#define PL011_LCR_SPS 0x80 /* Stick parity select */
|
||||
#define PL01X_LCR_WLEN 0x60 /* Mask of size bits */
|
||||
#define PL01X_LCR_8BITS 0x60 /* 8 bits per serial word */
|
||||
#define PL01X_LCR_7BITS 0x40 /* 7 bits */
|
||||
#define PL01X_LCR_6BITS 0x20 /* 6 bits */
|
||||
#define PL01X_LCR_5BITS 0x00 /* 5 bits */
|
||||
#define PL01X_LCR_FEN 0x10 /* FIFO enable */
|
||||
#define PL01X_LCR_STP2 0x08 /* 2 stop bits per serial word */
|
||||
#define PL01X_LCR_EPS 0x04 /* Even parity select */
|
||||
#define PL01X_LCR_PEN 0x02 /* Parity enable */
|
||||
#define PL01X_LCR_PEVEN (PL01X_LCR_PEN | PL01X_LCR_EPS)
|
||||
#define PL01X_LCR_PODD PL01X_LCR_PEN
|
||||
#define PL01X_LCR_PNONE 0x00 /* No parity */
|
||||
#define PL01X_LCR_BRK 0x01 /* Break Control */
|
||||
|
||||
/* modem control register */
|
||||
#define MCR_RTS 0x02 /* Request To Send */
|
||||
#define MCR_DTR 0x01 /* Data Terminal Ready */
|
||||
#define PL01X_MCR_RTS 0x02 /* Request To Send */
|
||||
#define PL01X_MCR_DTR 0x01 /* Data Terminal Ready */
|
||||
|
||||
/* receive status register */
|
||||
|
||||
#define RSR_OE 0x08 /* Overrun Error */
|
||||
#define RSR_BE 0x04 /* Break */
|
||||
#define RSR_PE 0x02 /* Parity Error */
|
||||
#define RSR_FE 0x01 /* Framing Error */
|
||||
#define PL01X_RSR_OE 0x08 /* Overrun Error */
|
||||
#define PL01X_RSR_BE 0x04 /* Break */
|
||||
#define PL01X_RSR_PE 0x02 /* Parity Error */
|
||||
#define PL01X_RSR_FE 0x01 /* Framing Error */
|
||||
#define PL01X_RSR_ERROR (PL01X_RSR_OE | PL01X_RSR_BE | PL01X_RSR_PE | PL01X_RSR_FE)
|
||||
|
||||
/* flag register */
|
||||
#define FR_TXFE 0x80 /* Transmit fifo empty */
|
||||
#define FR_RXFF 0x40 /* Recive fifo full */
|
||||
#define FR_TXFF 0x20 /* Transmit fifo full */
|
||||
#define FR_RXFE 0x10 /* Receive fifo empty */
|
||||
#define FR_BUSY 0x08 /* Uart Busy */
|
||||
#define FR_DCD 0x04 /* Data carrier detect */
|
||||
#define FR_DSR 0x02 /* Data set ready */
|
||||
#define FR_CTS 0x01 /* Clear to send */
|
||||
#define PL01X_FR_RI 0x100 /* Ring Indicator */
|
||||
#define PL01X_FR_TXFE 0x080 /* Transmit fifo empty */
|
||||
#define PL01X_FR_RXFF 0x040 /* Recive fifo full */
|
||||
#define PL01X_FR_TXFF 0x020 /* Transmit fifo full */
|
||||
#define PL01X_FR_RXFE 0x010 /* Receive fifo empty */
|
||||
#define PL01X_FR_BUSY 0x008 /* Uart Busy */
|
||||
#define PL01X_FR_DCD 0x004 /* Data carrier detect */
|
||||
#define PL01X_FR_DSR 0x002 /* Data set ready */
|
||||
#define PL01X_FR_CTS 0x001 /* Clear to send */
|
||||
|
||||
/* modem status register */
|
||||
/* All deltas are from the last read of the MSR. */
|
||||
#define MSR_DCD FR_DCD
|
||||
#define MSR_DSR FR_DSR
|
||||
#define MSR_CTS FR_CTS
|
||||
#define PL01X_MSR_DCD PL01X_FR_DCD
|
||||
#define PL01X_MSR_DSR PL01X_FR_DSR
|
||||
#define PL01X_MSR_CTS PL01X_FR_CTS
|
||||
|
||||
/* All interrupt status/clear registers */
|
||||
#define PL011_INT_OE 0x400
|
||||
#define PL011_INT_BE 0x200
|
||||
#define PL011_INT_PE 0x100
|
||||
#define PL011_INT_FE 0x080
|
||||
#define PL011_INT_RT 0x040
|
||||
#define PL011_INT_TX 0x020
|
||||
#define PL011_INT_RX 0x010
|
||||
#define PL011_INT_DSR 0x008
|
||||
#define PL011_INT_DCD 0x004
|
||||
#define PL011_INT_CTS 0x002
|
||||
#define PL011_INT_RIR 0x001
|
||||
|
||||
/* DMA control registers */
|
||||
#define PL011_DMA_ONERR 0x4
|
||||
#define PL011_DMA_TXE 0x2
|
||||
#define PL011_DMA_RXE 0x1
|
||||
|
||||
/* Register offsets */
|
||||
#define plcom_dr 0x00
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: plcom_ifpga.c,v 1.11 2011/07/01 20:39:34 dyoung Exp $ */
|
||||
/* $NetBSD: plcom_ifpga.c,v 1.12 2012/05/14 19:40:06 skrll Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 ARM Ltd
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
/* Interface to plcom (PL010) serial driver. */
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: plcom_ifpga.c,v 1.11 2011/07/01 20:39:34 dyoung Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: plcom_ifpga.c,v 1.12 2012/05/14 19:40:06 skrll Exp $");
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/device.h>
|
||||
|
|
@ -106,20 +106,20 @@ static void plcom_ifpga_set_mcr(void *aux, int unit, u_int mcr)
|
|||
|
||||
switch (unit) {
|
||||
case 0:
|
||||
if (mcr & MCR_RTS)
|
||||
if (mcr & PL01X_MCR_RTS)
|
||||
set |= IFPGA_SC_CTRL_UART0RTS;
|
||||
else
|
||||
clr |= IFPGA_SC_CTRL_UART0RTS;
|
||||
if (mcr & MCR_DTR)
|
||||
if (mcr & PL01X_MCR_DTR)
|
||||
set |= IFPGA_SC_CTRL_UART0DTR;
|
||||
else
|
||||
clr |= IFPGA_SC_CTRL_UART0DTR;
|
||||
case 1:
|
||||
if (mcr & MCR_RTS)
|
||||
if (mcr & PL01X_MCR_RTS)
|
||||
set |= IFPGA_SC_CTRL_UART1RTS;
|
||||
else
|
||||
clr |= IFPGA_SC_CTRL_UART1RTS;
|
||||
if (mcr & MCR_DTR)
|
||||
if (mcr & PL01X_MCR_DTR)
|
||||
set |= IFPGA_SC_CTRL_UART1DTR;
|
||||
else
|
||||
clr |= IFPGA_SC_CTRL_UART1DTR;
|
||||
|
|
|
|||
Loading…
Reference in New Issue