- Allocate interrupt handles dynamically from a pool(9) to reduce the
number of TLB misses during interrupt dispatch.
- Fully support evcnt(9) in all interrupt dispatchers.
- sysfpga_sreset()
Hit the soft-reset register to reset the board.
- sysfpga_twinkle_led()
Might as well put the blinkenlight on the Cayman to good use as
a "heartbeat" indicator.
This merge changes the device switch tables from static array to
dynamically generated by config(8).
- All device switches is defined as a constant structure in device drivers.
- The new grammer ``device-major'' is introduced to ``files''.
device-major <prefix> char <num> [block <num>] [<rules>]
- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.
- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.
- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.
- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.
- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.
- Set up a Panic Stack,
- Don't pre-map the sysfpga at this time.
- Calculate the CPU speed only if SH5_CPU_SPEED isn't defined.
- On a related note, make the CPU speed probing code more accurate.
- Print the CPU speed at startup.
- Force RB_SINGLE for now, at least until I get a bootloader written.
should have been bus_space_write_stream_2().
The sm(4) driver gets a bit further now.
While I'm here, g/c a debug printf accidentally commited last time around.
The latter's probe doesn't pick up the ethernet controller, and the
attach function needs to set MIIF_NOISOLATE.
We attach it at superio mainly because they share the same region of
address space, and the ethernet controller's interrupt is routed
through the superio.
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
