Commit Graph

709 Commits

Author SHA1 Message Date
jdolecek f5599abc0a fix typo 2001-09-23 19:59:19 +00:00
simonb 808d23f484 {,u}intptr_t are longs; adjust printf/scanf formats. 2001-09-19 05:23:43 +00:00
thorpej 3792a5d8c5 Add code to frob the MTRR-like registers on the AMD K6-2
and AMD K6-III.
2001-09-19 01:26:18 +00:00
thorpej d941f3b164 Define UWCCR bits for the AMD K6 (these are its MTRR-like registers). 2001-09-19 00:31:21 +00:00
thorpej f0d792297e Define the AMD K6 cache/write-combinding control register MSR. 2001-09-19 00:30:11 +00:00
jmc 9185cf1b34 Add mtrr.h to INCS list to get installed on a make includes 2001-09-12 04:44:21 +00:00
chris 0e7661f023 Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.
2001-09-10 21:19:08 +00:00
fvdl 78742dd0e0 Add flag to indicate that a process set some mtrrs that need to be
cleaned up automatically on exit.
2001-09-10 10:11:21 +00:00
fvdl c823d05ca0 Add definitions for mtrr syscalls. 2001-09-10 10:10:57 +00:00
fvdl e0a68652a8 MTRR include file, based on the one by Bill Sommerfeld from the i386 mp
branch.
2001-09-10 10:10:33 +00:00
perry edea1a2c17 Make it possible to query each battery individually by making the
APM_IOC_GETPOWER ioctl read/write. Setting the batteryid in the passed
structure returns the data for just that battery. The old ioctl
remains for binary compatibility but has been renamed.

Itojun already did the hard work -- I just added a couple of lines.

reviewed by: thorpej
2001-09-10 05:23:30 +00:00
thorpej 47920741b0 Implement bus_space_mmap(). 2001-09-04 02:37:08 +00:00
chs 9fa41ab3b9 use cli/sti instead of splhigh/splx for MCOUNT_ENTER/MCOUNT_EXIT.
this makes clearer how much time mcount() is really taking.
2001-08-23 06:17:00 +00:00
chs 7c661278ee update some comments. 2001-08-12 00:20:32 +00:00
thorpej 518ad20222 Upon further reading of the manual, don't save the MXCSR-at-last-exception.
Its status bits are sticky, and unaffacted by FNINIT.
2001-08-03 01:46:08 +00:00
thorpej 099e93139b In setregs(), initialize the process's MXCSR to the reset-default
value as documented in the IA-32 Instruction Set Reference (in the
description of the LDMXCSR insn).
2001-08-03 01:24:39 +00:00
thorpej f72ee0a9c6 Remember the MXCSR at last-exception the way we do the FPU SW/TW. 2001-08-03 01:11:49 +00:00
groo 3f5acd41c2 Remove trailing "U" on KERNBASE introduced in last commit.
Breaks assembly of locore.
2001-08-03 01:03:10 +00:00
thorpej 6e331fdd9f Define KERNTEXTOFF in terms of KERNBASE. 2001-08-03 00:47:59 +00:00
thorpej f0449fd933 - Rename cpu_use_fxsave to i386_use_fxsave.
- If we detect SSE/SSE2 support in the CPU, enable SSE exceptions
  and set i386_has_{sse,sse2} as appropriate.
- Expose i386_use_fxsave and i386_has_{sse,sse2} through sysctl
  as machdep.{osfsxr,sse,sse2}.
2001-08-02 22:04:28 +00:00
thorpej 99a7f640fe Add support for saving/restoring SSE/SSE2 state using FXSAVE/FXRSTOR.
Reviewed by Frank.
2001-08-02 21:04:43 +00:00
thorpej 4b584bf5bb Add several more Intel cache info entries, and fetch the CFLUSH
line size if we have the CFLUSH insn.
2001-08-01 19:50:48 +00:00
thorpej ebbd9cd428 Add some more CPUID feature bits. 2001-08-01 18:47:38 +00:00
thorpej c43f8649d2 Set up function pointers for copyin/copyout in preparation for
adding optimized versions for various CPU classes/models.

Split the 386 version of copyout into a separate routine, and
add a 486 version that doesn't have the class/page-writeability
check.
2001-07-31 18:28:58 +00:00
itojun 71aa31a75a support multiple batteries (currently only # of batteris is visible -
need to tweak ioctl API more).  PR 10545.
2001-07-22 16:05:17 +00:00
wiz a9356936b4 seperate -> separate 2001-07-22 13:33:58 +00:00
thorpej babefc5331 Add BUS_DMA_READ and BUS_DMA_WRITE flags, that hint the back-end
at dmamap load time that the mapping will be used for a unidirectional
transfer of the specified direction.
2001-07-19 15:32:10 +00:00
fvdl d68e2c3f12 Redefine evil tXXX register offset defines into the trapframe structure
to use offsetof. These should be completely nuked.

Fixes math_emulate lossage.
2001-07-17 08:13:06 +00:00
thorpej 091e29f94f In i386_softintr_lock(), use splserial() rather than splhigh(),
because of splhigh() braindamage on the i386 port.

Fixes port-i386/13038 and port-i386/12985.
2001-07-16 16:53:00 +00:00
christos 825843808a add MACHO_MACHDEP_CASES 2001-07-14 03:05:51 +00:00
christos 747d93e317 new i386 files for macho and mach. 2001-07-14 02:04:25 +00:00
christos 75dabe22c7 Use global descriptor 7 for mach traps. Unfortunately this is already
used by apm 16 bit code segments so we cannot have both at the same time.
2001-07-14 02:02:45 +00:00
thorpej e26fe5cc01 Compute the VM_* constants directly, rather than hard-coding
them (with the formulas in comments).
2001-06-25 16:28:48 +00:00
wiz f3f6c5b675 `accessible' only has one `a'. 2001-06-19 12:52:20 +00:00
fvdl b4b5dc533d Add fxsr CR4 bits. 2001-06-19 09:12:49 +00:00
sommerfeld 7e7d262c34 Add %fs/%gs to trap frame and save/restore them on
trap/interrupt/syscall entry from userspace.

Remove special-case "by hand" validation of fs/gs register values as
well as special handling of them in various signal handling paths.

Now, like %ds and %es, they are validated by the hardware on return to
userland.

This paves the way for the use of %fs for per-cpu data on
multiprocessor systems, and fixes an otherwise difficult-to-fix
interaction between threads/clone(2) and USER_LDT.

Discussed in advance with Frank van der Linden.
2001-06-17 21:01:32 +00:00
thorpej 8eb3b954f1 Don't need to prototype child_return() here, it's in <sys/proc.h>. 2001-06-14 22:56:55 +00:00
simonb e5bd00e48d For ports that wire up pciide in compatibility mode, have
them define __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
in pci_machdep.h and pciide_map_compat_intr() only calls
pciide_machdep_compat_intr_establish() if that preprocessor
define exists.

Ports that don't need to do this no longer need to supply a
dummy function.
2001-06-08 04:48:54 +00:00
lukem 178aeb74a0 work around lint issue (inspired by similar work in sparc port) 2001-06-07 04:44:05 +00:00
mrg 67afbd6270 use _KERNEL_OPT 2001-05-30 11:57:16 +00:00
chs 118ddca24a replace {simple_,}lock{_data,}_t with struct {simple,}lock {,*}. 2001-05-26 16:32:40 +00:00
perry c8057dc287 remove needless externs in front of function prototypes 2001-05-21 04:47:35 +00:00
thorpej 5c15afd718 Rearrange the cache info fetching code some more, and add support
for fetching cache info for AMD processors.
2001-05-03 00:35:37 +00:00
thorpej f89ed957f1 - Keep cache/tlb info in the cpu_info structure.
- Add "associativity" to the cache_info structure.
- Add a (*cpu_cacheinfo)() function pointer, like we have a
  (*cpu_setup)() function pointer.  Cache info in the `cpuid'
  is vendor-specific.
2001-05-02 21:07:01 +00:00
jdolecek 8aa43b5a54 The system configuration block structure doesn't need to be public 2001-05-02 13:16:33 +00:00
jdolecek 0b26347639 Add support for getting %es value from the bios call. 2001-05-02 13:12:45 +00:00
thorpej cf67ac7122 Per discussion w/ chuck and chuck, restructure the md page stuff
to use a structure called "vm_page_md", and use __HAVE_VM_PAGE_MD
and __HAVE_PMAP_PHYSSEG.
2001-05-01 02:19:13 +00:00
lukem b8f8cf0235 remove some lint, including ansifying some inlines 2001-04-30 01:17:30 +00:00
thorpej 2b27ac7a99 Add a VM_MDPAGE_MEMBERS macro that defines pmap-specific data for
each vm_page structure.  Add a VM_MDPAGE_INIT() macro to init this
data when pages are initialized by UVM.  These macros are mandatory,
but ports may #define them to nothing if they are not needed/used.

This deprecates struct pmap_physseg.  As a transitional measure,
allow a port to #define PMAP_PHYSSEG so that it can continue to
use it until its pmap is converted to use VM_MDPAGE_MEMBERS.

Use all this stuff to eliminate a lot of extra work in the Alpha
pmap module (it's smaller and faster now).  Changes to other pmap
modules will follow.
2001-04-29 22:44:31 +00:00
thorpej cb648add29 The idle loop page zero'er no longer needs to do uncached access
now that we have page coloring.
2001-04-29 04:42:04 +00:00