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Add several more Intel cache info entries, and fetch the CFLUSH 

line size if we have the CFLUSH insn.
This commit is contained in:
thorpej 2001-08-01 19:50:48 +00:00
parent ebbd9cd428
commit 4b584bf5bb
2 changed files with 62 additions and 2 deletions
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61
sys/arch/i386/i386/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.448 2001/07/31 18:28:59 thorpej Exp $ */
/* $NetBSD: machdep.c,v 1.449 2001/08/01 19:50:48 thorpej Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2000 The NetBSD Foundation, Inc.
@ -978,9 +978,17 @@ static const struct i386_cache_info intel_cpuid_cache_info[] = {
{ CAI_DCACHE,
0x0c,
16 * 1024, 2, 32 },
#if 0
/*
* Just ignore this entry. What is actually means is:
*
* No 2nd-level cacle, or if processor contains a valid
* 2nd-level cache, no 3rd-level cache.
*/
{ CAI_L2CACHE,
0x40,
0, 1, 0 },
#endif
{ CAI_L2CACHE,
0x41,
128 * 1024, 4, 32 },
@ -996,9 +1004,52 @@ static const struct i386_cache_info intel_cpuid_cache_info[] = {
{ CAI_L2CACHE,
0x45,
2 * 1024 * 1024, 4, 32 },
/*
* XXX Need a way to represent the following:
*
* 0x50: ITLB: 4K and 2M/4M, 64 entries
* 0x51: ITLB: 4K and 2M/4M, 128 entries
* 0x52: ITLB: 4K and 2M/4M, 285 entries
* 0x5b: DTLB: 4K and 4M, 64 entries
* 0x5b: DTLB: 4K and 4M, 128 entries
* 0x5d: DTLB: 4K and 4M, 256 entries
*/
{ CAI_DCACHE,
0x66,
8 * 1024, 4, 64 },
{ CAI_DCACHE,
0x67,
16 * 1024, 4, 64 },
{ CAI_DCACHE,
0x68,
32 * 1024, 4, 64 },
/*
* XXX Need a way to represent the following:
*
* 0x70: Trace cache, 12KuOP, 4-way
* 0x71: Trace cache, 16KuOP, 4-way
* 0x72: Trace cache, 32KuOP, 4-way
*
* Do we care?
*/
{ CAI_L2CACHE,
0x79,
128 * 1024, 8, 64 },
{ CAI_L2CACHE,
0x7a,
256 * 1024, 8, 64 },
{ CAI_L2CACHE,
0x7b,
512 * 1024, 8, 64 },
{ CAI_L2CACHE,
0x7c,
1 * 1024 * 1024, 8, 64 },
{ CAI_L2CACHE,
0x82,
256 * 1024, 8, 32 },
{ CAI_L2CACHE,
0x83,
512 * 1024, 8, 32 },
{ CAI_L2CACHE,
0x84,
1 * 1024 * 1024, 8, 32 },
@ -1017,6 +1068,14 @@ intel_cpuid_cpu_cacheinfo(struct cpu_info *ci)
int iterations, i, j;
u_int8_t desc;
/*
* If we have the CFLUSH insn, fetch the CFLUSH line size.
*/
if (cpu_feature & CPUID_CFLUSH) {
do_cpuid(1, descs);
ci->ci_cflush_lsize = ((descs[1] >> 8) & 0xff) * 8;
}
/*
* Parse the cache info from `cpuid'.
* XXX This is kinda ugly, but hey, so is the architecture...

3
sys/arch/i386/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.72 2001/06/14 22:56:56 thorpej Exp $ */
/* $NetBSD: cpu.h,v 1.73 2001/08/01 19:50:49 thorpej Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@ -80,6 +80,7 @@ struct cpu_info {
u_long ci_simple_locks; /* # of simple locks held */
#endif
u_int ci_cflush_lsize; /* CFLUSH insn line size */
struct i386_cache_info ci_cinfo[CAI_COUNT];
};