Commit Graph

13 Commits

Author SHA1 Message Date
he
ed9b489c17 Adapt to -Wcast-qual by adding a few consts. 2005-06-05 11:35:09 +00:00
chs
a73e314137 de-__P, remove register, ansify. 2005-01-19 01:58:21 +00:00
mycroft
c618f2cc87 Comprehensive patches from Christian Limpach:
* Fix problems with the DMA and SCSI drivers.
* Make turbo machines sort of work.
Additional fixes from me:
* Determine if we're a turbo at boot time, by looking at the ROM machine type.
* Set the display size correctly (1120 pixels wide, but padded to 1152 only on
  non-turbo machines).
Caveats:
* SCSI doesn't work on the turbo (or at least it blows chunks with no devices
  attached).
* Media selection doesn't work on the turbo (the BMAP stuff doesn't exist on
  turbo machines).
* The boot block is prone to timing out.
2002-09-11 01:46:29 +00:00
christos
f12f20db6c Apply patches from Christian Limpach:
- NeXT label reading support
    - SCSI dma fixes
    - media support for if_xe.c

Some of these need more cleanup, but at least make SCSI support usable on
the NeXT.
2002-07-11 16:03:09 +00:00
dbj
45ec8742b1 minor rework of dma driver
now uses the DMACSR_READ bit and no longer keeps _nd_dmadir in softc
unified transfer cleanup code, now in routine next_dma_finish_xfer()
fixed bounds checking on registers after transfer.
removed checking for bus errors since the bit is always set on some nexts
(specifically, on mourning, a 25mhz 68040 mono slab)
fixed a couple of dma bugs involving chaining dma buffers.
1999-08-29 05:56:26 +00:00
dbj
3c215084bc discovered the purpose of another bit in the dma control register.
DMACSR_READ is now a CSR status bit which can be used to know if current transfer is
from cpu to device.
the old DMACSR_READ bit is renamed DMACSR_SETREAD.  This is a control bit that tells
the dma transfer to be from cpu to device.
1999-08-28 09:19:04 +00:00
dbj
705311bcee resync bus_dma functions with current alpha versions.
added a field to a dma segment to return the actual length of that segment that
was successfully transferred.
1999-08-03 09:16:00 +00:00
dbj
00c8d4dd90 changed dma start alignment from 4 to 16 so that the cache flush
functions always have cache line aligned segments.
continued experimentation with scsi driver.
1999-03-14 10:31:05 +00:00
dbj
bb8f1300ce moved declaration of nextdma_intr into correct header file. 1999-03-04 14:18:25 +00:00
dbj
d3e627398e changed register for start of dma buffer to be DD_NEXT_INITBUF instead
of DD_NEXT for regular dma transfers, and not just ethernet transmit.
Keep track of dma read/write direction and set it each time we start or
restart dma.  This allows scsi to work, and doesn't appear to hinder ethernet.
1998-12-30 03:05:29 +00:00
dbj
db8bf6a623 Revamped DMA interface to unify chaining and non-chaining dma sequences.
Updated ethernet driver to work with new interface.
Continue work on esp driver.
1998-12-19 09:31:44 +00:00
dbj
023ee4f133 Started the esp scsi driver.
Fixed bus_space_handle_t in nextdma device.
Fixed scsi interrupt define.
1998-07-05 07:53:44 +00:00
dbj
ddff5f8e94 Initial import of NetBSD/next68k. 1998-06-09 07:53:05 +00:00