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57495 Commits

Author SHA1 Message Date
pooka
2bc5807797 Add FORK_CLEANFILES flag to fork1(), which makes the new process start out 
with a clean descriptor set (ie. not copied or shared from parent).

for rfork()
 2002-08-06 13:58:08 +00:00
grant
3273a7757a add X note comment for INSECURE option. 
addresses port-i386/17853 from hclsmith@yahoo.ca.
 2002-08-06 12:09:42 +00:00
shin
b0d22e8404 fix CPU_ROOT_DEVICE implementation. 2002-08-06 06:54:36 +00:00
shin
d4552e01aa compilation fix. 2002-08-06 06:52:49 +00:00
chs
d3c3fef89b add code from tsubai to handle the second CPU on openpic machines. 
the second CPU on dual G4 boxes works now.
while I'm here, use mfmsr() and mtmsr() instead of inline asms.
 2002-08-06 06:26:19 +00:00
chs
f7fb853264 be sure to re-enable interrupts before calling trap() a second time 
due to an AST.  the rule is that we must always have interrupts
enabled when acquiring kernel_lock, so that we can process blocking IPIs
from another CPU which is already holding kernel_lock.
reduce differences between the MP and non-MP versions of this file.
 2002-08-06 06:21:58 +00:00
chs
f73abf90fb on MP systems, if the firmware didn't configure the L2 cache 
on the non-boot CPUs, copy the L2CR configuration from the boot CPU.
also, fix the code that configures the L2 cache so that it works at all.
while I'm here, use mfspr() and mtspr() instead of inline asms.
 2002-08-06 06:20:08 +00:00
chs
2928d8ba05 actually we shouldn't hold kernel_lock while calling postsig(). 2002-08-06 06:18:24 +00:00
chs
0924752f24 add the MSSCR0 register and some more L2CR fields. 2002-08-06 06:17:50 +00:00
chs
461184c6b6 fix the calculation of the address of the IPI dispatch register. 2002-08-06 06:16:42 +00:00
chs
ef0d8145a7 avoid races in mp_save_{fpu,vec}_proc() where the other CPU 
dumps the state out from under us.
 2002-08-06 06:16:04 +00:00
chs
301f1ebf31 move more inlines to cpu.h: mftb(), mftbl() and mfpvr(). 
(the mftb() in pmap.c only wanted the lower 32 bits, so that's now mftbl()).
 2002-08-06 06:14:33 +00:00
itojun
cf8807954f backout previous. i was looking at the wrong RFC. 2002-08-06 04:58:57 +00:00
itojun
fa5ffb82e4 based on RFC2529, stf(4) should have 1480 as MTU, not 1280. 
tron found it, sync w/kame
 2002-08-05 23:37:48 +00:00
bjh21
a69295fb3b Enable csc(4), since it's reported as working. 2002-08-05 23:30:44 +00:00
bjh21
ed8346a525 Rather than forcing on XS_POLL in SCSI transfers ourselves, set 
SCSIPI_ADAPT_POLL_ONLY to tell the MI scsipi layer to do it for us.  This,
plus G/Cing some debugging code, removes the card-specific scsi_request
wrappers.
 2002-08-05 23:30:04 +00:00
soren
9e129fde67 Add ATA SMART reporting support from Ben Collver in kern/12787. 2002-08-05 23:29:27 +00:00
fredette
16cf89e5a5 Made changes in where/how the kernel is linked, and how the pmap 
maps it with BTLB entries, to minimize the number of BTLB entries
needed.

Because the CPU type was often guessed incorrectly, the mapping of
HP board number to system name now includes information about the
expected CPU type.
 2002-08-05 20:58:35 +00:00
fredette
190541e99d Poll the PDC console less frequently. 2002-08-05 20:38:35 +00:00
fredette
3295720e1a Don't use ldcw, since netisr might not be 16-byte aligned. 
Instead, disable interrupts and do a load and a store.
 2002-08-05 20:23:56 +00:00
shin
a59d490375 * add CPU_MIPS_NO_LLSC to Toshiba TX3912, TX3922, TX3927. 
* fix mips_has_llsc calculation logic.
 2002-08-05 13:02:40 +00:00
shin
2f33f11745 ++CPU_MAXID for CPU_LLSC. 2002-08-05 13:00:47 +00:00
onoe
248c861292 Fix IBSS for awi driver. 2002-08-05 06:55:05 +00:00
enami
a55bfb4d51 A cosmetic change. 2002-08-05 02:56:58 +00:00
enami
1aaddc3669 - Care about carry bit when adding short value to force 4 byte boundary. 
It may contain any 32 bit value there.
- Use correct instruction to clear carry bit.
- Don't use series of load with update instruction.  It's slower.
 2002-08-05 02:55:39 +00:00
simonb
f068458085 The TX79 core in the R5900 doesn't support LL/SC. 
XXX: Others in this table will need to be updated.
 2002-08-05 02:18:43 +00:00
simonb
fef76c7e26 Use a __HAVE_BOOTINFO_H define to check for bootinfo support instead of 
speading port names in arch-dependant code.
 2002-08-05 02:13:14 +00:00
simonb
bf71dff7b9 Convert to use merged mips cpu_sysctl(). 2002-08-05 01:33:36 +00:00
itojun
dc8b2582ca backout previous 2002-08-05 01:16:59 +00:00
simonb
d67404d97e Fix tyop. 2002-08-05 01:15:22 +00:00
itojun
08a994ac23 soekris device use 19200bps on boot, it seems 2002-08-05 01:14:58 +00:00
thorpej
82421f1fdb Regen; added ADI BECC product ID. 2002-08-04 21:47:58 +00:00
thorpej
4da9d49d31 Add product ID for the ADI i80200 Big Endian Companion Chip. 2002-08-04 21:47:25 +00:00
thorpej
22e32aa941 #if 0 the stray interrupt messages -- we tend to get them "a lot" 
during normal activity on some IOP310-based designs.
 2002-08-04 17:52:46 +00:00
uwe
5b89d2589b In DIAGNOSTIC kernels detect situation that on sun4m neither hardware 
nor software interrupt pending bit is set for the current ipl.  Report
this as a "bogus" interrupt (better name anyone?).  This is a symptom
of a bug in interrupt handling in one of device drivers interrupting
at this ipl.  Reviewed by pk.
 2002-08-04 14:57:34 +00:00
simonb
6fbeccd902 Make this compile for the non-sbmips case. 2002-08-04 14:42:56 +00:00
isaki
2997fb2d61 Fix printf format in DIAGNOSTIC. 2002-08-04 13:08:29 +00:00
soren
5eb191755a _PC_MAX_CANON and _PC_MAX_INPUT aren't really filesystem-specific in NetBSD. 2002-08-04 05:42:43 +00:00
oster
2a9c8b7cfd One less debug option. 2002-08-04 03:33:04 +00:00
oster
522009f8a9 Nuke some unneeded #includes. 2002-08-04 03:27:04 +00:00
oster
1387eac16b Remove a couple of options that are obsolete. 2002-08-04 03:26:39 +00:00
oster
6ad082845f Let's just say that the way things were stored in the array for the 
debugging buffer made it much less useful than it appears.  More memory
for other things now.
 2002-08-04 03:22:07 +00:00
gmcgarry
460c8c3adc mipsco and sgimips also implement bootinfo, but didn't provide 
the CPU_BOOTED_KERNEL sysctl variable.
 2002-08-04 03:16:19 +00:00
gmcgarry
7470337484 Move LLSC feature test for mips1 to cputab[]. 2002-08-04 02:27:51 +00:00
thorpej
0aa15bdf33 Add support for "xor5", "xor6", "xor7", and "xor8". 2002-08-04 02:26:18 +00:00
thorpej
16003abd0f Add standard names for 5-, 6-, 7-, and 8-way XOR. 2002-08-04 02:17:06 +00:00
thorpej
4c1506f740 *Actually return* EINVAL when the output stream UIO's I/O is larger 
than SSIZE_MAX.
 2002-08-04 01:52:00 +00:00
gmcgarry
617f58fb55 Add sysctl variable to represent native CPU support for LL/SC instructions. 2002-08-04 01:47:15 +00:00
gmcgarry
886e32d355 mips1 doesn't have native LL/SC instructions. 2002-08-04 01:43:03 +00:00
gmcgarry
3647e0d293 Merge cpu_sysctl() for all mips ports, based on powerpc and m68k precedent. 
For now, only pmax implements CPU_BOOTED_KERNEL.  Need to revisit.
 2002-08-04 01:41:23 +00:00