1035faff1d
writable, not writeable.
2003-01-06 20:30:28 +00:00
dbb0f0ebed
Use aprint_normal() for cfprint routines.
2003-01-01 01:47:30 +00:00
4a06119a9d
Pass the system call table to trace_enter() and ktrsys() so that it is
...
possible to use alternate system call tables. This is usefull for
displaying correctly the arguments in Mach binaries traces.
If NULL is given, then the regular systam call table for the process is used.
2002-12-21 16:23:56 +00:00
5b6caeca74
Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't
...
require flushing (even in the instruction cache handlers). This gives
about a 4% improvement in a "make depend" benchmark.
Mark the SB-1 CPUs as having a fully coherent data cache that only
require flushing in the instruction cache handlers. This gives about
a 5% improvement in a "make depend" benchmark.
2002-12-17 12:07:50 +00:00
2c1a832f25
Add support for caches where the data cache is fully coherent, and
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either requires flushing either only when the I cache ops are used
or not at all. Currently only used by MIPS32/MIPS64 cache code.
2002-12-17 12:04:29 +00:00
e8cc3884de
Rename __LDPGSZ to AOUT_LDPGSZ, to accurately reflect what it is.
2002-12-10 17:14:02 +00:00
78ea2dd367
Use __LDPGSZ (which must be == USRTEXT) as the text address for a.out
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executables, and eliminate the USRTEXT constant, which was only used
by the a.out exec code.
2002-12-10 05:14:24 +00:00
6a5e492b57
Remove the explicit `makeoptions MACHINE_ARCH="mipse{b,l}"' for kernel
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builds and use the endianness of the toolchain being used to determine
the endianness of the kernel.
2002-12-09 22:54:09 +00:00
699bf96665
Drop the _KERNEL test; these functions are needed for SMP and other ports
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don't bother with a _KERNEL check.
2002-12-05 02:56:51 +00:00
d03ac2a783
Fix botch in previous. This is pcb.h, not reg.h.
2002-11-30 22:50:01 +00:00
9a87c0933c
make LKM friedlier - only include opt_* ifdef _KERNEL_OPT
2002-11-30 10:52:16 +00:00
fdd1e3b715
Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.
2002-11-30 01:52:31 +00:00
d644dd9c43
Add multiple-inclusion protection.
2002-11-30 01:49:18 +00:00
0635de35a3
Remove KDIR=, since SYS_INCLUDE=symlinks and KDIR are not supported any more.
2002-11-26 23:30:07 +00:00
12c35ee2d2
New generic way-aware MIPS32/64 range-index cache functions with proper
...
handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.
Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.
2002-11-24 07:41:29 +00:00
3a72aadc2b
Add the VI bit in config 0.
2002-11-24 07:28:42 +00:00
3682edd3d4
Move the curpcb and segbase extern decls to cpu.h to better group together
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what will need to change for SMP.
Hide 'struct cpu_info' and some macros in #ifdef _KERNEL/#endif.
2002-11-24 07:26:04 +00:00
8935916d0a
initial support for mac features in new chip revs
2002-11-19 01:44:04 +00:00
5e3d4a224c
Add cache_r4k_op_8lines_{16,32} macros to perform cache ops on 8
...
consecutive lines.
2002-11-17 06:40:43 +00:00
aa5595f691
Fix typo in the address of the Au1500 MAC1 enable register; 2nd MAC works
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on the Au1500 cpu now.
2002-11-17 04:57:34 +00:00
ba1c8ffa9d
Remove reference to mips_int5_evcnt from here; that is port-specific,
...
not arch-specific.
2002-11-17 04:56:57 +00:00
d584ed9598
Add a realcode argument to trace_enter and ktrsyscall. realcode is the
...
original system call number, which can be negative for a Mach trap.
We cannot just replace code by realcode, because ktrsyscall uses it as
an index in the system call table, thus crashing the kernel when the
value is negative.
2002-11-15 20:06:00 +00:00
5bdb1a36ce
Add a hack to mipsNN_pdcache_wbinv_range_index_32_4way() so that we
...
use the index ops at a offset of the page size as well, controlled by
an MIPS64_SB1 check. The SB1 D-cache way size is physically indexed
and twice as big as the page size (4k), so we weren't flushing all the
addresses we needed too.
XXX: This is kinda gross; will be cleaned up and made more generic soon.
There are still other SB1-specific issues to be cleaned up too...
2002-11-15 01:23:17 +00:00
181d7f08c9
Use COP0_HAZARD_FPUENABLE instead of a hard-coded 4 NOPs when enabling
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the FPU.
2002-11-15 01:16:18 +00:00
2aabe4d4e2
Define COP0_HAZARD_FPUENABLE as four nops.
...
Include <mips/sb1regs.h> if MIPS64_SB1 is defined.
2002-11-15 01:15:11 +00:00
383afcb5b6
Declare some CP0 hazards for the SB1 core.
2002-11-15 01:09:20 +00:00
28a1083dd2
Put the MIPS64_SB1 option in opt_cputype.h.
2002-11-15 01:02:49 +00:00
3d416825dc
White space nits.
2002-11-15 00:58:32 +00:00
abad61e77f
Remove o32 stack layout exposure form cpu_fork().
...
Tested on R4000 and R3000.
2002-11-12 14:00:41 +00:00
96c9d84cda
Add support for the ST M41T81 RTC found on pass 2 swarm boards.
...
XXX: Much of this should live in arch/sbmips instead of arch/mips/sibyte.
XXX: These should be replaced with MI SMBus drivers one day.
2002-11-12 01:22:25 +00:00
aba5de5e41
Remove a PARANOIADIAG check which is a bit too paranoid. This one
...
would now trigger whenever a previously used "cached" uarea was reused.
Reviewed by thorpej and chs.
2002-11-11 22:30:15 +00:00
396f36cc12
Fix a typo in the on-board device selection machinery (which I thought
...
I'd committed long ago).
2002-11-11 16:39:18 +00:00
2e98091daf
Make sure we use index ops (instead of hit ops) in the range index
...
functions.
Fix typos in the cache_r4k_op_32_4way_load_off macro.
Both problems reported by Chris Demetriou.
2002-11-10 11:11:39 +00:00
b8eff8f9aa
Adapt for the ioctl ERESTART/EPASSTHROUGH changes.
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Make sure we don't tsleep() at splhigh/splserial.
2002-11-10 11:06:11 +00:00
6fb837941b
Remove some copyright notices that don't apply to this code.
2002-11-10 11:01:15 +00:00
983202f1ed
Change pmap_kenter_pa/pmap_kremove pair back to pmap_enter/pmap_remove
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in fear of the case choosen kva results in occupying inconsistent
distinctive cache lines of uva.
2002-11-10 05:29:18 +00:00
2a312dd17f
Use pmap_enter_pa and pmap_kremove for vmapbuf/vunmapbuf, respectively.
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Have variable names renamed for the logic clarity.
2002-11-10 02:27:50 +00:00
84ccc9c46e
Build with kernel with -msoft-float.
2002-11-09 20:34:26 +00:00
ff114c4a59
Fix signed/unsigned comparison warnings.
2002-11-09 20:06:07 +00:00
21ca5cbcc7
Make md_ss_addr a vaddr_t.
2002-11-09 20:05:57 +00:00
800f626770
Fix signed/unsigned comparison warnings.
2002-11-09 20:00:20 +00:00
0c2979d1c8
Fix signed/unsigned comparison warnings.
2002-11-09 19:35:52 +00:00
4d7f6969a5
Make cache size/mask variables unsigned.
2002-11-09 19:34:39 +00:00
73f78d5e61
Fix signed/unsigned comparison warnings.
2002-11-09 18:52:20 +00:00
3689b18f89
* Add -mno-abicalls to AFLAGS.
...
* GCC 3.3's traditional preprocessor functions properly now, so we
no longer need to special-case it.
2002-11-09 18:18:22 +00:00
a99bec6b60
Nuke the CROSSDIR stuff.
2002-11-09 18:12:09 +00:00
94df053502
Nuke "mips_reg_t" exposures from here. "mips_reg_t" will be
...
corrected-back with "register_t" by completing the implementations
of N32 and LP64 environment.
2002-11-09 10:59:52 +00:00
e935239e3c
No need to pass -mno-half-pic; NetBSD's compiler does not generate
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half-pic references.
2002-11-09 07:31:08 +00:00
31fcce3c41
Include <sys/device.h> so this compiles again.
2002-11-09 04:13:03 +00:00
8d6e18f90d
- Make monolistic files into smaller manageable pieces, resulting
...
three new files;
sig_machdep.c (from mips_machdep.c)
copy.S and sigcode.S (from locore.S)
- Nuke the local use of struct sigframe, which is now identical to
struct sigcontext, from sendsig() as the consequence of new signal
trampoline.
2002-11-09 02:02:31 +00:00
wiz