Begin conditioning device configuration on revision number. Four
revisions are known:
1.1/1.5 -> ADM8211A,
2.0 -> ADM8211B,
3.0 -> ADM8211C.
The B and C parts, which are not supported yet, have AP capability.
attachment instead of dereferencing NULL and so
(this needs a serious cleanup -- the framework was thought to be generally
usable for ~all PCI ISDN cards; this didn't work out, so we are left
with a lot of nonsense to support just 1 particular card type...)
the chipset revision - by pci_find_device().
While the latter isn't better technically (works around the otherwise
hierarchical device tree), using it doesn't require PCI configuration
functions to support stuff which philosophically doesn't belong there.
So we get the hands free to restructure things for better loadable
driver support.
(Actually, since this is about chipset internal IDE interfaces where
the PCI device/function numbers are well known, this all is unnecessary.)
esa_round_blocksize().
- Fix esa_trigger_output() and esa_trigger_input() to initialise the
channel's buffer/block size using the supplied parameters.
- While here, simplify esa_intr().
This gets kphone working on my esa(4)-equipped laptop.
i386/identcpu.c renders it counterproductive.
(this was the only use and the reason for the invention of the
SKIP_FUNCn quirk; it should probably be removed entirely).
This is only usable with some caution because these soundcards only
allow to map IO port 0x20x for this, thus bypassing PCI address
management. Very likely this will only work on primary PCI buses, and there
is some potential for conflicts with ISA devices as well.
(XXX cannot be detached because the "joy" driver doesn't support it yet)
Hack the match function to accept an alternate Atheros vendor ID by munging it
to look like the expected one. This is needed for DWL-G520 cards (which
otherwise "just work").
may retry it as a memory read multiple command under some circumstances.
This can totally confuse some PCI controllers, so ensure that it
will never do this by making sure that the Read Threshold (FIFO
Read Request Control) field of the FIFO Valid Byte Count and Control
registers for both channels (BA5 offset 0x40 and 0x44) are set to
be at least as large as the cacheline size register (the unit of
measure for these registers is 32 bytes).
