Keep track of what we set the interrupt mask to, rather than reading it from
the chip.
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parent
e3694d0dc1
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673c114d25
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@ -1,4 +1,4 @@
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/* $NetBSD: if_bce.c,v 1.4 2004/04/23 16:03:33 joda Exp $ */
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/* $NetBSD: if_bce.c,v 1.5 2004/07/09 05:08:22 mycroft Exp $ */
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/*
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* Copyright (c) 2003 Clifford Wright. All rights reserved.
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@ -130,6 +130,7 @@ struct bce_softc {
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struct bce_dma_slot *bce_tx_ring; /* transmit ring */
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struct bce_chain_data bce_cdata; /* mbufs */
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bus_dmamap_t bce_ring_map;
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u_int32_t bce_intmask; /* current intr mask */
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u_int32_t bce_rxin; /* last rx descriptor seen */
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u_int32_t bce_txin; /* last tx descriptor seen */
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int bce_txsfree; /* no. tx slots available */
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@ -679,7 +680,6 @@ bce_intr(xsc)
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struct bce_softc *sc;
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struct ifnet *ifp;
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u_int32_t intstatus;
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u_int32_t intmask;
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int wantinit;
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int handled = 0;
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@ -690,11 +690,9 @@ bce_intr(xsc)
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for (wantinit = 0; wantinit == 0;) {
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intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
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BCE_INT_STS);
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intmask = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
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BCE_INT_MASK);
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/* ignore if not ours, or unsolicited interrupts */
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intstatus &= intmask;
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intstatus &= sc->bce_intmask;
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if (intstatus == 0)
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break;
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@ -1000,8 +998,10 @@ bce_init(ifp)
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}
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/* Enable interrupts */
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sc->bce_intmask =
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I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO;
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bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK,
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I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO);
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sc->bce_intmask);
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/* start the receive dma */
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bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR,
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@ -1129,7 +1129,8 @@ bce_stop(ifp, disable)
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/* Disable interrupts. */
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bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0);
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bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK);
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sc->bce_intmask = 0;
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delay(10);
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/* Disable emac */
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bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED);
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