bus_space_handle_t now holds an address and two ASIs, one for normal accesses
and one for streaming accesses. This allows to map individual handles
different ways, so some can use MMU bypass accesses and others use virtual
addresses. bus_space_map() will now create handles that use bypass accesses
unles BUS_SPACE_MAP_LINEAR is passed in. So only pass in BUS_SPACE_MAP_LINEAR
if you absolutely *need* to use bus_space_vaddr(). This removes at least one
extra level of indirection and should reduce TLB misses.
32-bit kernels have problems accessing 64-bit addresses, so they always use
virtual addresses.
If __PCI_DEV_FUNCORDER is defined, don't do the song-and-dance to check if
a device is multi-function; machdep code is going to tell us exactly which
functions to probe.
Note this required changing how pci_func_devorder() works in the
sparc64 PCI machdep code; now the "curnode" is assumed to point
to the bus, rather than some function (typically 0) on the device,
just as pci_bus_devorder() makes that assumption.
All this should allow the PCI code to actually locate the second
HME device on a Sun Netra t1, which is at 3,1 -- previously, the
PCI code would have missed it because there is no device at 3,0.
(Sun deserves a brick to the head for this one -- this seems clearly
out of line with the PCI spec.)
occur if SPDB_CONF (and hence DEBUG). also convert the panic in
pci_conf_write() to a SPDB_CONF warning and a return.
this cleans up pcictl(8) support.
interrupt number. properly find interrupts for the E250. modify
pci_intr_map() accordingly. retire psycho_intr_map(). deal with
INO values upto 0x3f, not upto 0x32. restructure sabre_init() and
psycho_init() to be more similar, and display each psycho's IGN.
psycho_intr_establish() deals with INO upto 0x3f, values from 0x32
and higher get 0 for IPL.
tested on E250 & U5.
pci_attach_args *" instead of from four separate parameters which in
all cases were extracted from the same "struct pci_attach_args".
This both simplifies the driver api, and allows for alternate PCI
interrupt mapping schemes, such as one using the tables described in
the Intel Multiprocessor Spec which describe interrupt wirings for
devices behind pci-pci bridges based on the device's location rather
the bridge's location.
Tested on alpha and i386; welcome to 1.5Q
in the parent bus format (i.e. an INO) rather than being represented as
an PCI interrupt line. Provide a hack to work around this in pci_attach_hook().
<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>
also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.
the arguments are changed so the address is first and the ASI second so we
can have the address in %o0:%o1 and not worry about unused registers.
Also a bit of copyright cleanup.
(`SUNW,sabre') for now, and it doesn't really quite work there yet anyway.
the bus space/dma code is cloned from the sbus driver. the IOMMU code also
is cloned from the sbus code, but separated out into iommu.c so that we can
share it with the sbus driver. hopefully, much of the bus space/dma code
can also be re-shared with the sbus driver and the ebus driver but for now
these copies will do.
support for the real UltraSPARC PCI (`SUNW,psycho') is unwritten, though
most of this code is shared with it.
we can probe PCI config space and try to configue devices, but interrupts
don't work yet...
eeh