on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
which indicates that VIPT cache on the CPU could cause virtual alias
and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
might cause virtual alias if mips_cache_virtual_alias is true.
(note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
by new mips_cache_virtual_alias.
While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.
Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.
XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)
* For sparc64 and amd64, define *SIZ32 VM constants.
* Add a new function pointer to struct emul, pointing at a function
that will return the default VM map address. The default function
is uvm_map_defaultaddr, which just uses the VM_DEFAULT_ADDRESS
macro. This gives emulations control over the default map address,
and allows things to be mapped at the right address (in 32bit range)
for COMPAT_NETBSD32.
* Add code to adjust the data and stack limits when a COMPAT_NETBSD32
or COMPAT_SVR4_32 binary is executed.
* Don't use USRSTACK in kern_resource.c, use p_vmspace->vm_minsaddr
instead (emulations might have set it differently)
* Since this changes struct emul, bump kernel version to 3.99.2
Tested on amd64, compile-tested on sparc64.
attimer(4) is the new body of the part of pcppi(4) that mapped the TIMER1
register to set the pitch of the bell. It was necessary to separate them
in order to have a working ACPI attachment (as the two appear as different
devices in the ACPI structures).
too disordered. This should improve file creation speed on aged filesystems.
Include code to disorder the list for debugging purposes, though this is
of course not compiled in by default.
with options PCI_NETBSD_CONFIGURE.
Patch from KIYOHARA Takashi on port-cobalt.
This change makes siop(4) (and maybe all other PCI devices
using pci mem space) work on cobalt.
