passed which is larger than an int but has int alignment. As well as
fixing the described problem, this is the same way it is handled in the
Irix and Ultrix header files.
Problem and suggested solution by Uros Prestor in port-mips mailling
list.
remove some checks for impossible conditions.
in pmap_enter(), only call pmap_remove() to remove an existing mapping
if there actually is an existing mapping.
in pmap_remove_pv(), don't flush the MIPS1 cache when removing the last mapping.
this was added in rev 1.97, to avoid stale data being left in the cache
when the page is zeroed bypassing the cache in pmap_zero_page_uncached().
we've since found that bypassing the cache for idle-loop page zeroing
doesn't work very well anyway, so we don't do that anymore.
so now we can remove the extra cache-flush.
remove pmap_zero_page_uncached() while I'm thinking of it.
various other cleanup.
interrupt to sneak in after EXL had been set; the interrupt EPC was stale
as PC isn't saved if EXL is set, causing the eret to return to the wrong
place and leading to kernel-mode TLB misses on user addresses. The bug
was discovered by the japanese NetBSD/*mips folks and the same fix was
found independently by shinohara-san (shin@netbsd.org).
- Use pools for pmap structures and pv_entry structures.
- Remove a bunch of splvm()/splx(), no longer needed now that
pmap_kenter_pa() and pmap_kremove() are as they should be.
Mostly from Chuck Silvers.
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).
These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.
distinguished by SYSID register in the system controller. Note
that PRiD 0x20 is for a standalone RC32364 processor which has the
same 32300 core inside. Rather better to name them MIPS32 ISA.
simonb