(Sorry for a big commit, I can't separate this into several pieces...)
Pls check sys/netinet6/TODO and sys/netinet6/IMPLEMENTATION for details.
- sys/kern: do not assume single mbuf, accept chained mbuf on passing
data from userland to kernel (or other way round).
- "midway" ATM card: ATM PVC pseudo device support, like those done in ALTQ
package (ftp://ftp.csl.sony.co.jp/pub/kjc/).
- sys/netinet/tcp*: IPv4/v6 dual stack tcp support.
- sys/netinet/{ip6,icmp6}.h, sys/net/pfkeyv2.h: IETF document assumes those
file to be there so we patch it up.
- sys/netinet: IPsec additions are here and there.
- sys/netinet6/*: most of IPv6 code sits here.
- sys/netkey: IPsec key management code
- dev/pci/pcidevs: regen
In my understanding no code here is subject to export control so it
should be safe.
Anne Hutton <hutton@isi.edu>]:
- add support for Adaptec 155 PCI ATM cards (e.g. ANA-5940)
- add sc->is_adaptec to handle differences between cards.
- break out MID_MK_TXQ/MID_MK_RXQ seperate macros to handle
the new Adaptec format TXQ/RXQ.
- adjust en_dqneed to return 1 on ADP (since the Adaptec can
DMA anything in one DRQ/DTQ!)
- add hook for a bus specific reset function (adaptec has
a seperate reset register that needs to be hit when
resettting the midway).
- adjust DMA test to not worry about burst sizes on the
adaptec (since it handles it all for us!) and to handle
the new DTQ/DRQ format.
- add Adaptec DMA support to en_txlaunch() and en_service()
BUG FIXES:
- fixed receiver panic under heavy load ("lost mbuf in slot 0!").
when the reassembly buffer overflows, the T-bit is set in
the RDB and the data field is empty. en_service() sets up
a 4-byte (RDB size) dummy DMA without IF_ENQUEUE. but the
recv intr handling in en_intr() always does IF_DEQUEUE.
as a result, a successive recv intr loses its mbuf and
leads to a panic. the solution is to only IF_DEQUEUE if
the interrupt has non-zero length (indicating that there
is an mbuf to get). in order for this to work, EN_DQ_MK
must always be non-zero. we do this by or'ing in an unused
bit (0x80000).
reported by: Kenjiro Cho <kjc@csl.sony.co.jp>
- fix setting of transmit channel when txspeed[] is non-zero
(e.g. traffic shaping). the old scheme didn't work
properly (it allowed the same VCI to use multiple tx channels
thus defeating the txspeed[] parameter). the new scheme
statically assigns a VC to a channel when txspeed[] is set.
[note that the code to set txspeed[] isn't in the driver right
now since a MI interface to do this hasn't been made yet]
we add sc->txvc2slot[] and sc->txslot[n].nref for this.
reported by: Kenjiro Cho <kjc@csl.sony.co.jp>,
Milind M Buddihikot <milind@ccrc.wustl.edu>,
Dong Lin <dong@eecs.harvard.edu>
- when doing SRAM copies, be sure to round up the length to the next
largest word (otherwise the driver will try to do a byte clean
up DMA and then get an ID error interrupt).
MINOR CLEANUPS:
- clean up loops in DMA test
contributed by: Kenjiro Cho <kjc@csl.sony.co.jp>
- restructure and cleanup of en_read/en_write macros/inlines
- clean up some byte ordering stuff so that we are consistant throughout
the driver
- No more distinction between i/o-mapped and memory-mapped
devices. It's all "bus space" now, and space tags
differentiate the space with finer grain than the
bus chipset tag.
- Add memory barrier methods.
- Implement space alloc/free methods.
- Implement region read/write methods (like memcpy to/from
bus space).
This interface provides a better abstraction for dealing with
machine-independent chipset drivers.
- merged multiple DRQ/DTQ ADD macros into a single DRQ and a single DTQ
macro with a uniform interface to make the code simpler and easier to read.
- en_start: only update atm_flags if EN_MBUF_OPT is enabled (which it
should be)
- for alburst: make sure we don't DMA more bytes than we need (on both
tx and rx). if the alburst is larger than we need, drop to
MIDDMA_WORD mode.
- major change: enable the use of byte and 2 byte DMA on the trasmit side.
this allows us to DMA from non-word sized/aligned mbufs directly.
[the old code would always call en_mfix which would copy (or move) the
data in order to ensure proper alignment... it turns out TCP gives
us non-word sized/aligned mbufs when it is retransmitting, so we needed
to handle this case more efficiently.] the following functions
were changed to make this work:
- en_dqneed: add an arg to let us know if we are transmitting or not.
if we are TX, then we must take into account byte DMAs when
estimating the number of DTQs we will need for a buffer
- en_start: only mfix mbufs if DMA is disabled
- en_txdma: only set launch.nodma if we have en_mfix'd the mbuf chain
also, we may need a DTQ to flush the chip's internal byte buffer
- en_txlaunch: only attempt a copy if we have the proper alignment.
add byte dma code for the front and end of the buffer.
make sure the internal dma buffer is flushed out.
- stats: keep track of how many times we have to use byte sized DMA
midwayreg:
- add byte/2byte DMA defines
midwayvar:
- add new stat counter to monitor less-than-word lengthed DMA
[1] rxslot "cur" pointer wasn't updated if we copied all data and
didn't have any fill. this could cause a service id mismatch
panic under load.
[2] recv of aal0 forgot to include the cell header in the data length
calc [add cell header length to midwayreg.h]
[3] fix control info "chop" for raw mode and aal0
[4] handle rxsb better for native atm connections
(XXX: still working on this ... not complete and needs revision)
itojun