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New bus.h implementation/interface:

Browse Source 
- No more distinction between i/o-mapped and memory-mapped
	  devices.  It's all "bus space" now, and space tags
	  differentiate the space with finer grain than the
	  bus chipset tag.
	- Add memory barrier methods.
	- Implement space alloc/free methods.
	- Implement region read/write methods (like memcpy to/from
	  bus space).
This interface provides a better abstraction for dealing with
machine-independent chipset drivers.
This commit is contained in:
thorpej 1996-10-21 22:24:37 +00:00
parent 18a4f7f093
commit 16c4c5af26
29 changed files with 1251 additions and 724 deletions
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14
sys/arch/i386/i386/apm.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: apm.c,v 1.11 1996/10/16 22:30:34 jtk Exp $ */
/* $NetBSD: apm.c,v 1.12 1996/10/21 22:24:37 thorpej Exp $ */
/*-
* Copyright (c) 1995,1996 John T. Kohl. All rights reserved.
@ -53,6 +53,7 @@
#include <sys/poll.h>
#include <sys/conf.h>
#include <machine/bus.h>
#include <machine/stdarg.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
@ -866,12 +867,13 @@ apmattach(parent, self, aux)
/*
* need page zero or biosbasemem area mapping.
*/
bus_mem_handle_t memh;
bus_space_handle_t memh;
/* XXX cheat and use knowledge of
bus_mem_map() implementation on i386 */
(void) bus_mem_map(0, apminfo.apm_data_seg_base,
apminfo.apm_data_seg_len, 0, &memh);
DPRINTF((": mapping bios data area %x @ %p\n%s",
bus_space_map() implementation on i386 */
(void) bus_space_map(I386_BUS_SPACE_MEM,
apminfo.apm_data_seg_base,
apminfo.apm_data_seg_len, 0, &memh);
DPRINTF((": mapping bios data area %x @ 0x%lx\n%s",
apminfo.apm_data_seg_base, memh,
apmsc->sc_dev.dv_xname));
setsegment(&dynamic_gdt[GAPMDATA_SEL].sd,

335
sys/arch/i386/i386/machdep.c
View File

@ -1,7 +1,8 @@
/* $NetBSD: machdep.c,v 1.212 1996/10/17 19:31:09 fvdl Exp $ */
/* $NetBSD: machdep.c,v 1.213 1996/10/21 22:24:38 thorpej Exp $ */
/*-
* Copyright (c) 1993, 1994, 1995, 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Jason R. Thorpe. All rights reserved.
* Copyright (c) 1992 Terrence R. Lambert.
* Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
* All rights reserved.
@ -157,11 +158,17 @@ static vm_offset_t avail_next;
* storage for 8 regions in each, initially. Later, ioport_malloc_safe
* will indicate that it's safe to use malloc() to dynamically allocate
* region descriptors.
*
* N.B. At least two regions are _always_ allocated from the iomem
* extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM).
*
* The extent maps are not static! Machine-dependent ISA and EISA
* routines need access to them for bus address space allocation.
*/
static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
static struct extent *ioport_ex;
static struct extent *iomem_ex;
struct extent *ioport_ex;
struct extent *iomem_ex;
static ioport_malloc_safe;
caddr_t allocsys __P((caddr_t));
@ -173,6 +180,9 @@ void consinit __P((void));
static int exec_nomid __P((struct proc *, struct exec_package *));
#endif
int bus_mem_add_mapping __P((bus_addr_t, bus_size_t,
int, bus_space_handle_t *));
/*
* Machine-dependent startup code
*/
@ -1122,11 +1132,16 @@ init386(first_avail)
* Note: we don't have to check the return value since
* creation of a fixed extent map will never fail (since
* descriptor storage has already been allocated).
*
* N.B. The iomem extent manages _all_ physical addresses
* on the machine. When the amount of RAM is found, the two
* extents of RAM are allocated from the map (0 -> ISA hole
* and end of ISA hole -> end of RAM).
*/
ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF,
(caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
iomem_ex = extent_create("iomem", 0x0a0000, 0x100000, M_DEVBUF,
iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF,
(caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage),
EX_NOCOALESCE|EX_NOWAIT);
@ -1197,6 +1212,24 @@ init386(first_avail)
biosextmem = EXTMEM_SIZE;
#endif
/*
* Allocate the physical addresses used by RAM from the iomem
* extent map. This is done before the addresses are
* page rounded just to make sure we get them all.
*/
if (extent_alloc_region(iomem_ex, 0, IOM_BEGIN, EX_NOWAIT)) {
/* XXX What should we do? */
printf("WARNING: CAN'T ALLOCATE BASE RAM FROM IOMEM EXTENT MAP!\n");
}
avail_end = biosextmem ? IOM_END + biosextmem * 1024
: biosbasemem * 1024; /* just temporary use */
if (avail_end > IOM_END && extent_alloc_region(iomem_ex, IOM_END,
(avail_end - IOM_END), EX_NOWAIT)) {
/* XXX What should we do? */
printf("WARNING: CAN'T ALLOCATE EXTENDED MEMORY FROM IOMEM EXTENT MAP!\n");
}
/* Round down to whole pages. */
biosbasemem &= -(NBPG / 1024);
biosextmem &= -(NBPG / 1024);
@ -1459,59 +1492,167 @@ cpu_reset()
}
int
bus_mem_map(t, bpa, size, cacheable, mhp)
bus_chipset_tag_t t;
bus_mem_addr_t bpa;
bus_mem_size_t size;
bus_space_map(t, bpa, size, cacheable, bshp)
bus_space_tag_t t;
bus_addr_t bpa;
bus_size_t size;
int cacheable;
bus_mem_handle_t *mhp;
bus_space_handle_t *bshp;
{
u_long pa, endpa;
vm_offset_t va;
int error, did_extent_alloc = 0;
int error;
struct extent *ex;
/*
* Pick the appropriate extent map.
*/
switch (t) {
case I386_BUS_SPACE_IO:
ex = ioport_ex;
break;
case I386_BUS_SPACE_MEM:
ex = iomem_ex;
break;
default:
panic("bus_space_map: bad bus space tag");
}
/*
* Before we go any further, let's make sure that this
* memory region is available.
*
* XXX We check for free space if the requested region
* XXX only if the request is within the ISA memory hole.
* XXX This is arguably bogus.
* region is available.
*/
if (bpa >= iomem_ex->ex_start && bpa < iomem_ex->ex_end) {
error = extent_alloc_region(iomem_ex, bpa, size,
EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0));
if (error)
return (error);
did_extent_alloc = 1;
error = extent_alloc_region(ex, bpa, size,
EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0));
if (error)
return (error);
/*
* For I/O space, that's all she wrote.
*/
if (t == I386_BUS_SPACE_IO) {
*bshp = bpa;
return (0);
}
/*
* For memory space, map the bus physical address to
* a kernel virtual address.
*/
error = bus_mem_add_mapping(bpa, size, cacheable, bshp);
if (error) {
if (extent_free(ex, bpa, size, EX_NOWAIT |
(ioport_malloc_safe ? EX_MALLOCOK : 0))) {
printf("bus_space_map: pa 0x%lx, size 0x%lx\n",
bpa, size);
printf("bus_space_map: can't free region\n");
}
}
return (error);
}
int
bus_space_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
bpap, bshp)
bus_space_tag_t t;
bus_addr_t rstart, rend;
bus_size_t size, alignment;
bus_addr_t boundary;
int cacheable;
bus_addr_t *bpap;
bus_space_handle_t *bshp;
{
struct extent *ex;
u_long bpa;
int error;
/*
* Pick the appropriate extent map.
*/
switch (t) {
case I386_BUS_SPACE_IO:
ex = ioport_ex;
break;
case I386_BUS_SPACE_MEM:
ex = iomem_ex;
break;
default:
panic("bus_space_alloc: bad bus space tag");
}
/*
* Sanity check the allocation against the extent's boundaries.
*/
if (rstart < ex->ex_start || rend > ex->ex_end)
panic("bus_space_alloc: bad region start/end");
/*
* Do the requested allocation.
*/
error = extent_alloc_subregion(ex, rstart, rend, size, alignment,
boundary, EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0),
&bpa);
if (error)
return (error);
/*
* For I/O space, that's all she wrote.
*/
if (t == I386_BUS_SPACE_IO) {
*bshp = *bpap = bpa;
return (0);
}
/*
* For memory space, map the bus physical address to
* a kernel virtual address.
*/
error = bus_mem_add_mapping(bpa, size, cacheable, bshp);
if (error) {
if (extent_free(iomem_ex, bpa, size, EX_NOWAIT |
(ioport_malloc_safe ? EX_MALLOCOK : 0))) {
printf("bus_space_alloc: pa 0x%lx, size 0x%lx\n",
bpa, size);
printf("bus_space_alloc: can't free region\n");
}
}
*bpap = bpa;
return (error);
}
int
bus_mem_add_mapping(bpa, size, cacheable, bshp)
bus_addr_t bpa;
bus_size_t size;
int cacheable;
bus_space_handle_t *bshp;
{
u_long pa, endpa;
vm_offset_t va;
pa = i386_trunc_page(bpa);
endpa = i386_round_page((bpa + size) - 1);
#ifdef DIAGNOSTIC
if (endpa <= pa)
panic("bus_mem_map: overflow");
panic("bus_mem_add_mapping: overflow");
#endif
va = kmem_alloc_pageable(kernel_map, endpa - pa);
if (va == 0) {
if (did_extent_alloc) {
if (extent_free(iomem_ex, bpa, size, EX_NOWAIT |
(ioport_malloc_safe ? EX_MALLOCOK : 0))) {
/* XXX panic? */
printf("bus_mem_map: pa 0x%lx, size 0x%lx\n",
bpa, size);
printf("bus_mem_map: can't free region\n");
}
}
return (1);
}
*mhp = (caddr_t)(va + (bpa & PGOFSET));
if (va == 0)
return (ENOMEM);
*bshp = (bus_space_handle_t)(va + (bpa & PGOFSET));
for (; pa < endpa; pa += NBPG, va += NBPG) {
pmap_enter(pmap_kernel(), va, pa, VM_PROT_READ | VM_PROT_WRITE,
TRUE);
pmap_enter(pmap_kernel(), va, pa,
VM_PROT_READ | VM_PROT_WRITE, TRUE);
if (!cacheable)
pmap_changebit(pa, PG_N, ~0);
else
@ -1522,75 +1663,73 @@ bus_mem_map(t, bpa, size, cacheable, mhp)
}
void
bus_mem_unmap(t, memh, size)
bus_chipset_tag_t t;
bus_mem_handle_t memh;
bus_mem_size_t size;
bus_space_unmap(t, bsh, size)
bus_space_tag_t t;
bus_space_handle_t bsh;
bus_size_t size;
{
vm_offset_t va, endva;
bus_mem_addr_t bpa;
va = i386_trunc_page(memh);
endva = i386_round_page((memh + size) - 1);
#ifdef DIAGNOSTIC
if (endva <= va)
panic("bus_mem_unmap: overflow");
#endif
struct extent *ex;
u_long va, endva;
bus_addr_t bpa;
/*
* Find the PA the mapping corresponds to and free that
* region from the iomem extent map.
*
* XXX We only do this for regions that lie within the
* XXX ISA memory hole. This is arguably bogus.
* Find the correct extent and bus physical address.
*/
bpa = pmap_extract(pmap_kernel(), va) + ((u_long)memh & PGOFSET);
if (bpa >= iomem_ex->ex_start && bpa < iomem_ex->ex_end) {
if (extent_free(iomem_ex, bpa, size,
EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) {
printf("bus_mem_unmap: pa %p, size 0x%lx\n",
memh, size);
printf("bus_mem_unmap: can't free region\n");
}
switch (t) {
case I386_BUS_SPACE_IO:
ex = ioport_ex;
bpa = bsh;
break;
case I386_BUS_SPACE_MEM:
ex = iomem_ex;
va = i386_trunc_page(bsh);
endva = i386_round_page((bsh + size) - 1);
#ifdef DIAGNOSTIC
if (endva <= va)
panic("bus_space_unmap: overflow");
#endif
bpa = pmap_extract(pmap_kernel(), va) + (bsh & PGOFSET);
/*
* Free the kernel virtual mapping.
*/
kmem_free(kernel_map, va, endva - va);
break;
default:
panic("bus_space_unmap: bad bus space tag");
}
kmem_free(kernel_map, va, endva - va);
if (extent_free(ex, bpa, size,
EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) {
printf("bus_space_unmap: %s 0x%lx, size 0x%lx\n",
(t == I386_BUS_SPACE_IO) ? "port" : "pa", bpa, size);
printf("bus_space_unmap: can't free region\n");
}
}
void
bus_space_free(t, bsh, size)
bus_space_tag_t t;
bus_space_handle_t bsh;
bus_size_t size;
{
/* bus_space_unmap() does all that we need to do. */
bus_space_unmap(t, bsh, size);
}
int
bus_io_map(t, port, size, iohp)
bus_chipset_tag_t t;
bus_io_addr_t port;
bus_io_size_t size;
bus_io_handle_t *iohp;
bus_space_subregion(t, bsh, offset, size, nbshp)
bus_space_tag_t t;
bus_space_handle_t bsh;
bus_size_t offset, size;
bus_space_handle_t *nbshp;
{
extern struct extent *ioport_ex;
int error;
error = extent_alloc_region(ioport_ex, port, size,
EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0));
if (error)
return (error);
*iohp = port;
*nbshp = bsh + offset;
return (0);
}
void
bus_io_unmap(t, ioh, size)
bus_chipset_tag_t t;
bus_io_handle_t ioh;
bus_io_size_t size;
{
extern struct extent *ioport_ex;
int error;
error = extent_free(ioport_ex, ioh, size,
EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0));
if (error) {
printf("bus_io_unmap: port 0x%lx, size 0x%lx\n",
ioh, size);
printf("bus_io_unmap: can't free region\n");
}
}

11
sys/arch/i386/i386/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.13 1996/10/13 03:19:47 christos Exp $ */
/* $NetBSD: mainbus.c,v 1.14 1996/10/21 22:24:40 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -106,7 +106,8 @@ mainbus_attach(parent, self, aux)
#if NPCI > 0
if (pci_mode_detect() != 0) {
mba.mba_pba.pba_busname = "pci";
mba.mba_pba.pba_bc = NULL;
mba.mba_pba.pba_iot = I386_BUS_SPACE_IO;
mba.mba_pba.pba_memt = I386_BUS_SPACE_MEM;
mba.mba_pba.pba_bus = 0;
config_found(self, &mba.mba_pba, mainbus_print);
}
@ -114,13 +115,15 @@ mainbus_attach(parent, self, aux)
if (!bcmp(ISA_HOLE_VADDR(EISA_ID_PADDR), EISA_ID, EISA_ID_LEN)) {
mba.mba_eba.eba_busname = "eisa";
mba.mba_eba.eba_bc = NULL;
mba.mba_eba.eba_iot = I386_BUS_SPACE_IO;
mba.mba_eba.eba_memt = I386_BUS_SPACE_MEM;
config_found(self, &mba.mba_eba, mainbus_print);
}
if (1 /* XXX ISA NOT YET SEEN */) {
mba.mba_iba.iba_busname = "isa";
mba.mba_iba.iba_bc = NULL;
mba.mba_iba.iba_iot = I386_BUS_SPACE_IO;
mba.mba_iba.iba_memt = I386_BUS_SPACE_MEM;
config_found(self, &mba.mba_iba, mainbus_print);
}
#if NAPM > 0

454
sys/arch/i386/include/bus.h
View File

@ -1,6 +1,8 @@
/* $NetBSD: bus.h,v 1.4 1996/06/23 19:59:06 thorpej Exp $ */
/* $NetBSD: bus.h,v 1.5 1996/10/21 22:26:19 thorpej Exp $ */
/*
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Jason R. Thorpe. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -36,82 +38,416 @@
#include <machine/pio.h>
/*
* I/O addresses (in bus space)
* Values for the i386 bus space tag, not to be used directly by MI code.
*/
typedef u_long bus_io_addr_t;
typedef u_long bus_io_size_t;
#define I386_BUS_SPACE_IO 0 /* space is i/o space */
#define I386_BUS_SPACE_MEM 1 /* space is mem space */
/*
* Memory addresses (in bus space)
* Bus address and size types
*/
typedef u_long bus_mem_addr_t;
typedef u_long bus_mem_size_t;
typedef u_long bus_addr_t;
typedef u_long bus_size_t;
/*
* Access methods for bus resources, I/O space, and memory space.
* Access methods for bus resources and address space.
*/
typedef void *bus_chipset_tag_t;
typedef u_long bus_io_handle_t;
typedef caddr_t bus_mem_handle_t;
typedef int bus_space_tag_t;
typedef u_long bus_space_handle_t;
int bus_io_map __P((bus_chipset_tag_t, bus_io_addr_t,
bus_io_size_t, bus_io_handle_t *));
void bus_io_unmap __P((bus_chipset_tag_t, bus_io_handle_t,
bus_io_size_t));
int bus_space_map __P((bus_space_tag_t t, bus_addr_t addr,
bus_size_t size, int cacheable, bus_space_handle_t *bshp));
void bus_space_unmap __P((bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t size));
int bus_space_subregion __P((bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp));
#define bus_io_read_1(t, h, o) ((void) t, inb((h) + (o)))
#define bus_io_read_2(t, h, o) ((void) t, inw((h) + (o)))
#define bus_io_read_4(t, h, o) ((void) t, inl((h) + (o)))
#if 0 /* Cause a link error for bus_io_read_8 */
#define bus_io_read_8(t, h, o) !!! bus_io_read_8 unimplemented !!!
int bus_space_alloc __P((bus_space_tag_t t, bus_addr_t rstart,
bus_addr_t rend, bus_size_t size, bus_size_t align,
bus_addr_t boundary, int cacheable, bus_addr_t *addrp,
bus_space_handle_t *bshp));
void bus_space_free __P((bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t size));
/*
* u_intN_t bus_space_read_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset));
*
* Read a 1, 2, 4, or 8 byte quantity from bus space
* described by tag/handle/offset.
*/
#define bus_space_read_1(t, h, o) \
((t) == I386_BUS_SPACE_IO ? (inb((h) + (o))) : \
(*(volatile u_int8_t *)((h) + (o))))
#define bus_space_read_2(t, h, o) \
((t) == I386_BUS_SPACE_IO ? (inw((h) + (o))) : \
(*(volatile u_int16_t *)((h) + (o))))
#define bus_space_read_4(t, h, o) \
((t) == I386_BUS_SPACE_IO ? (inl((h) + (o))) : \
(*(volatile u_int32_t *)((h) + (o))))
#if 0 /* Cause a link error for bus_space_read_8 */
#define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!!
#endif
#define bus_io_read_multi_1(t, h, o, a, c) \
((void) t, insb((h) + (o), (a), (c)))
#define bus_io_read_multi_2(t, h, o, a, c) \
((void) t, insw((h) + (o), (a), (c)))
#define bus_io_read_multi_4(t, h, o, a, c) \
((void) t, insl((h) + (o), (a), (c)))
#if 0 /* Cause a link error for bus_io_read_multi_8 */
#define bus_io_read_multi_8(t, h, o, a, c) \
!!! bus_io_read_multi_8 unimplemented !!!
/*
* void bus_space_read_multi_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* u_intN_t *addr, size_t count));
*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle/offset and copy into buffer provided.
*/
#define bus_space_read_multi_1(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
insb((h) + (o), (a), (c)); \
} else { \
__asm __volatile(" \
cld ; \
1: movb (%0),%%al ; \
stosb ; \
loop 1b" : \
: \
"r" ((h) + (o)), "D" ((a)), "c" ((c)) : \
"%edi", "%ecx", "%eax", "memory"); \
} \
} while (0)
#define bus_space_read_multi_2(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
insw((h) + (o), (a), (c)); \
} else { \
__asm __volatile(" \
cld ; \
1: movw (%0),%%ax ; \
stosw ; \
loop 1b" : \
: \
"r" ((h) + (o)), "D" ((a)), "c" ((c)) : \
"%edi", "%ecx", "%eax", "memory"); \
} \
} while (0)
#define bus_space_read_multi_4(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
insl((h) + (o), (a), (c)); \
} else { \
__asm __volatile(" \
cld ; \
1: movl (%0),%%eax ; \
stosl ; \
loop 1b" : \
: \
"r" ((h) + (o)), "D" ((a)), "c" ((c)) : \
"%edi", "%ecx", "%eax", "memory"); \
} \
} while (0)
#if 0 /* Cause a link error for bus_space_read_multi_8 */
#define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!!
#endif
#define bus_io_write_1(t, h, o, v) ((void) t, outb((h) + (o), (v)))
#define bus_io_write_2(t, h, o, v) ((void) t, outw((h) + (o), (v)))
#define bus_io_write_4(t, h, o, v) ((void) t, outl((h) + (o), (v)))
#if 0 /* Cause a link error for bus_io_write_8 */
#define bus_io_write_8(t, h, o, v) !!! bus_io_write_8 unimplemented !!!
/*
* void bus_space_read_region_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* u_intN_t *addr, size_t count));
*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle and starting at `offset' and copy into
* buffer provided.
*/
#define bus_space_read_region_1(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
__asm __volatile(" \
cld ; \
1: inb %w0,%%al ; \
stosb ; \
incl %0 ; \
loop 1b" : \
: \
"d" ((h) + (o)), "D" ((a)), "c" ((c)) : \
"%edx", "%edi", "%ecx", "%eax", "memory"); \
} else { \
__asm __volatile(" \
cld ; \
repne ; \
movsb" : \
: \
"S" ((h) + (o)), "D" ((a)), "c" ((c)) : \
"%esi", "%edi", "%ecx", "memory"); \
} \
} while (0)
#define bus_space_read_region_2(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
__asm __volatile(" \
cld ; \
1: inw %w0,%%ax ; \
stosw ; \
addl $2,%0 ; \
loop 1b" : \
: \
"d" ((h) + (o)), "D" ((a)), "c" ((c)) : \
"%edx", "%edi", "%ecx", "%eax", "memory"); \
} else { \
__asm __volatile(" \
cld ; \
repne ; \
movsw" : \
: \
"S" ((h) + (o)), "D" ((a)), "c" ((c)) : \
"%esi", "%edi", "%ecx", "memory"); \
} \
} while (0)
#define bus_space_read_region_4(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
__asm __volatile(" \
cld ; \
1: inl %w0,%%eax ; \
stosl ; \
addl $4,%0 ; \
loop 1b" : \
: \
"d" ((h) + (o)), "D" ((a)), "c" ((c)) : \
"%edx", "%edi", "%ecx", "%eax", "memory"); \
} else { \
__asm __volatile(" \
cld ; \
repne ; \
movsl" : \
: \
"S" ((h) + (o)), "D" ((a)), "c" ((c)) : \
"%esi", "%edi", "%ecx", "memory"); \
} \
} while (0)
#if 0 /* Cause a link error for bus_space_read_region_8 */
#define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!!
#endif
#define bus_io_write_multi_1(t, h, o, a, c) \
((void) t, outsb((h) + (o), (a), (c)))
#define bus_io_write_multi_2(t, h, o, a, c) \
((void) t, outsw((h) + (o), (a), (c)))
#define bus_io_write_multi_4(t, h, o, a, c) \
((void) t, outsl((h) + (o), (a), (c)))
#if 0 /* Cause a link error for bus_io_write_multi_8 */
#define bus_io_write_multi_8(t, h, o, a, c) \
!!! bus_io_write_multi_8 unimplimented !!!
/*
* void bus_space_write_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* u_intN_t value));
*
* Write the 1, 2, 4, or 8 byte value `value' to bus space
* described by tag/handle/offset.
*/
#define bus_space_write_1(t, h, o, v) do { \
if ((t) == I386_BUS_SPACE_IO) \
outb((h) + (o), (v)); \
else \
((void)(*(volatile u_int8_t *)((h) + (o)) = (v))); \
} while (0)
#define bus_space_write_2(t, h, o, v) do { \
if ((t) == I386_BUS_SPACE_IO) \
outw((h) + (o), (v)); \
else \
((void)(*(volatile u_int16_t *)((h) + (o)) = (v))); \
} while (0)
#define bus_space_write_4(t, h, o, v) do { \
if ((t) == I386_BUS_SPACE_IO) \
outl((h) + (o), (v)); \
else \
((void)(*(volatile u_int32_t *)((h) + (o)) = (v))); \
} while (0)
#if 0 /* Cause a link error for bus_space_write_8 */
#define bus_space_write_8 !!! bus_space_write_8 not implemented !!!
#endif
int bus_mem_map __P((bus_chipset_tag_t t, bus_mem_addr_t bpa,
bus_mem_size_t size, int cacheable, bus_mem_handle_t *mhp));
void bus_mem_unmap __P((bus_chipset_tag_t t, bus_mem_handle_t memh,
bus_mem_size_t size));
/*
* void bus_space_write_multi_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* u_intN_t *addr, size_t count));
*
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer
* provided to bus space described by tag/handle/offset.
*/
#define bus_mem_read_1(t, h, o) ((void) t, (*(volatile u_int8_t *)((h) + (o))))
#define bus_mem_read_2(t, h, o) ((void) t, (*(volatile u_int16_t *)((h) + (o))))
#define bus_mem_read_4(t, h, o) ((void) t, (*(volatile u_int32_t *)((h) + (o))))
#define bus_mem_read_8(t, h, o) ((void) t, (*(volatile u_int64_t *)((h) + (o))))
#define bus_space_write_multi_1(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
outsb((h) + (o), (a), (c)); \
} else { \
__asm __volatile(" \
cld ; \
1: lodsb ; \
movb %%al,(%0) ; \
loop 1b" : \
: \
"r" ((h) + (o)), "S" ((a)), "c" ((c)) : \
"%esi", "%ecx", "%eax"); \
} \
} while (0)
#define bus_mem_write_1(t, h, o, v) \
((void) t, ((void)(*(volatile u_int8_t *)((h) + (o)) = (v))))
#define bus_mem_write_2(t, h, o, v) \
((void) t, ((void)(*(volatile u_int16_t *)((h) + (o)) = (v))))
#define bus_mem_write_4(t, h, o, v) \
((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
#define bus_mem_write_8(t, h, o, v) \
((void) t, ((void)(*(volatile u_int64_t *)((h) + (o)) = (v))))
#define bus_space_write_multi_2(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
outsw((h) + (o), (a), (c)); \
} else { \
__asm __volatile(" \
cld ; \
1: lodsw ; \
movw %%ax,(%0) ; \
loop 1b" : \
: \
"r" ((h) + (o)), "S" ((a)), "c" ((c)) : \
"%esi", "%ecx", "%eax"); \
} \
} while (0)
#define bus_space_write_multi_4(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
outsl((h) + (o), (a), (c)); \
} else { \
__asm __volatile(" \
cld ; \
1: lodsl ; \
movl %%eax,(%0) ; \
loop 1b" : \
: \
"r" ((h) + (o)), "S" ((a)), "c" ((c)) : \
"%esi", "%ecx", "%eax"); \
} \
} while (0)
#if 0 /* Cause a link error for bus_space_write_multi_8 */
#define bus_space_write_multi_8(t, h, o, a, c) \
!!! bus_space_write_multi_8 unimplimented !!!
#endif
/*
* void bus_space_write_region_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* u_intN_t *addr, size_t count));
*
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
* to bus space described by tag/handle starting at `offset'.
*/
#define bus_space_write_region_1(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
__asm __volatile(" \
cld ; \
1: lodsb ; \
outb %%al,%w0 ; \
incl %0 ; \
loop 1b" : \
: \
"d" ((h) + (o)), "S" ((a)), "c" ((c)) : \
"%edx", "%esi", "%ecx", "%eax", "memory"); \
} else { \
__asm __volatile(" \
cld ; \
repne ; \
movsb" : \
: \
"D" ((h) + (o)), "S" ((a)), "c" ((c)) : \
"%edi", "%esi", "%ecx", "memory"); \
} \
} while (0)
#define bus_space_write_region_2(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
__asm __volatile(" \
cld ; \
1: lodsw ; \
outw %%ax,%w0 ; \
addl $2,%0 ; \
loop 1b" : \
: \
"d" ((h) + (o)), "S" ((a)), "c" ((c)) : \
"%edx", "%esi", "%ecx", "%eax", "memory"); \
} else { \
__asm __volatile(" \
cld ; \
repne ; \
movsw" : \
: \
"D" ((h) + (o)), "S" ((a)), "c" ((c)) : \
"%edi", "%esi", "%ecx", "memory"); \
} \
} while (0)
#define bus_space_write_region_4(t, h, o, a, c) do { \
if ((t) == I386_BUS_SPACE_IO) { \
__asm __volatile(" \
cld ; \
1: lodsl ; \
outl %%eax,%w0 ; \
addl $4,%0 ; \
loop 1b" : \
: \
"d" ((h) + (o)), "S" ((a)), "c" ((c)) : \
"%edx", "%esi", "%ecx", "%eax", "memory"); \
} else { \
__asm __volatile(" \
cld ; \
repne ; \
movsl" : \
: \
"D" ((h) + (o)), "S" ((a)), "c" ((c)) : \
"%edi", "%esi", "%ecx", "memory"); \
} \
} while (0)
#if 0 /* Cause a link error for bus_space_write_region_8 */
#define bus_space_write_region_8 \
!!! bus_space_write_region_8 unimplemented !!!
#endif
/*
* void bus_space_set_multi_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, u_intN_t val, size_t count));
*
* Write the 1, 2, 4, or 8 byte value `val' to bus space described
* by tag/handle/offset `count' times.
*/
/* XXX IMPLEMENT bus_space_set_multi_N() XXX */
/*
* void bus_space_set_region_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, u_intN_t val, size_t count));
*
* Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
* by tag/handle starting at `offset'.
*/
/* XXX IMPLEMENT bus_space_set_region_N() XXX */
/*
* void bus_space_copy_N __P((bus_space_tag_t tag,
* bus_space_handle_t bsh1, bus_size_t off1,
* bus_space_handle_t bsh2, bus_size_t off2,
* size_t count));
*
* Copy `count' 1, 2, 4, or 8 byte values from bus space starting
* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
*/
/* XXX IMPLEMENT bus_space_copy_N() XXX */
/*
* Bus read/write barrier methods.
*
* void bus_space_barrier __P((bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* bus_size_t len, int flags));
*
* Note: the i386 does not currently require barriers, but we must
* provide the flags to MI code.
*/
#define bus_space_barrier(t, h, o, l, f)
#define BUS_BARRIER_READ 0x01 /* force read barrier */
#define BUS_BARRIER_WRITE 0x02 /* force write barrier */
#endif /* _I386_BUS_H_ */

58
sys/arch/i386/isa/ahc_isa.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ahc_isa.c,v 1.4 1996/10/13 03:19:57 christos Exp $ */
/* $NetBSD: ahc_isa.c,v 1.5 1996/10/21 22:27:39 thorpej Exp $ */
/*
* Product specific probe and attach routines for:
@ -105,9 +105,9 @@
#define AHC_ISA_PRIMING_VID(index) (AHC_ISA_VID + (index))
#define AHC_ISA_PRIMING_PID(index) (AHC_ISA_PID + (index))
int ahc_isa_irq __P((bus_chipset_tag_t, bus_io_handle_t));
int ahc_isa_idstring __P((bus_chipset_tag_t, bus_io_handle_t, char *));
int ahc_isa_match __P((struct isa_attach_args *, bus_io_addr_t));
int ahc_isa_irq __P((bus_space_tag_t, bus_space_handle_t));
int ahc_isa_idstring __P((bus_space_tag_t, bus_space_handle_t, char *));
int ahc_isa_match __P((struct isa_attach_args *, bus_addr_t));
int ahc_isa_probe __P((struct device *, void *, void *));
void ahc_isa_attach __P((struct device *, struct device *, void *));
@ -137,15 +137,15 @@ static int ahc_isa_slot_initialized;
* Return irq setting of the board, otherwise -1.
*/
int
ahc_isa_irq(bc, ioh)
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
ahc_isa_irq(iot, ioh)
bus_space_tag_t iot;
bus_space_handle_t ioh;
{
int irq;
u_char intdef;
ahc_reset("ahc_isa", bc, ioh);
intdef = bus_io_read_1(bc, ioh, INTDEF);
ahc_reset("ahc_isa", iot, ioh);
intdef = bus_space_read_1(iot, ioh, INTDEF);
switch (irq = (intdef & 0xf)) {
case 9:
case 10:
@ -164,9 +164,9 @@ ahc_isa_irq(bc, ioh)
}
int
ahc_isa_idstring(bc, ioh, idstring)
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
ahc_isa_idstring(iot, ioh, idstring)
bus_space_tag_t iot;
bus_space_handle_t ioh;
char *idstring;
{
u_int8_t vid[EISA_NVIDREGS], pid[EISA_NPIDREGS];
@ -174,9 +174,9 @@ ahc_isa_idstring(bc, ioh, idstring)
/* Get the vendor ID bytes */
for (i = 0; i < EISA_NVIDREGS; i++) {
bus_io_write_1(bc, ioh, AHC_ISA_PRIMING,
bus_space_write_1(iot, ioh, AHC_ISA_PRIMING,
AHC_ISA_PRIMING_VID(i));
vid[i] = bus_io_read_1(bc, ioh, AHC_ISA_VID + i);
vid[i] = bus_space_read_1(iot, ioh, AHC_ISA_VID + i);
}
/* Check for device existence */
@ -198,9 +198,9 @@ ahc_isa_idstring(bc, ioh, idstring)
/* Get the product ID bytes */
for (i = 0; i < EISA_NPIDREGS; i++) {
bus_io_write_1(bc, ioh, AHC_ISA_PRIMING,
bus_space_write_1(iot, ioh, AHC_ISA_PRIMING,
AHC_ISA_PRIMING_PID(i));
pid[i] = bus_io_read_1(bc, ioh, AHC_ISA_PID + i);
pid[i] = bus_space_read_1(iot, ioh, AHC_ISA_PID + i);
}
/* Create the ID string from the vendor and product IDs */
@ -219,10 +219,10 @@ ahc_isa_idstring(bc, ioh, idstring)
int
ahc_isa_match(ia, iobase)
struct isa_attach_args *ia;
bus_io_addr_t iobase;
bus_addr_t iobase;
{
bus_chipset_tag_t bc = ia->ia_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ia->ia_iot;
bus_space_handle_t ioh;
int irq;
char idstring[EISA_IDSTRINGLEN];
@ -231,7 +231,7 @@ ahc_isa_match(ia, iobase)
* space. If we can't, assume nothing's there, but
* warn about it.
*/
if (bus_io_map(bc, iobase, AHC_ISA_IOSIZE, &ioh)) {
if (bus_space_map(iot, iobase, AHC_ISA_IOSIZE, 0, &ioh)) {
#if 0
/*
* Don't print anything out here, since this could
@ -244,15 +244,15 @@ ahc_isa_match(ia, iobase)
return (0);
}
if (!ahc_isa_idstring(bc, ioh, idstring))
if (!ahc_isa_idstring(iot, ioh, idstring))
irq = -1; /* cannot get the ID string */
else if (strcmp(idstring, "ADP7756") &&
strcmp(idstring, "ADP7757"))
irq = -1; /* unknown ID strings */
else
irq = ahc_isa_irq(bc, ioh);
irq = ahc_isa_irq(iot, ioh);
bus_io_unmap(bc, ioh, AHC_ISA_IOSIZE);
bus_space_unmap(iot, ioh, AHC_ISA_IOSIZE);
if (irq < 0)
return (0);
@ -336,17 +336,17 @@ ahc_isa_attach(parent, self, aux)
ahc_type type;
struct ahc_data *ahc = (void *)self;
struct isa_attach_args *ia = aux;
bus_chipset_tag_t bc = ia->ia_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ia->ia_iot;
bus_space_handle_t ioh;
int irq;
char idstring[EISA_IDSTRINGLEN];
const char *model;
if (bus_io_map(bc, ia->ia_iobase, ia->ia_iosize, &ioh))
if (bus_space_map(iot, ia->ia_iobase, ia->ia_iosize, 0, &ioh))
panic("ahc_isa_attach: could not map slot I/O addresses");
if (!ahc_isa_idstring(bc, ioh, idstring))
if (!ahc_isa_idstring(iot, ioh, idstring))
panic("ahc_isa_attach: could not read ID string");
if ((irq = ahc_isa_irq(bc, ioh)) < 0)
if ((irq = ahc_isa_irq(iot, ioh)) < 0)
panic("ahc_isa_attach: ahc_isa_irq failed!");
if (strcmp(idstring, "ADP7756") == 0) {
@ -360,7 +360,7 @@ ahc_isa_attach(parent, self, aux)
}
printf(": %s\n", model);
ahc_construct(ahc, bc, ioh, type, AHC_FNONE);
ahc_construct(ahc, iot, ioh, type, AHC_FNONE);
#ifdef DEBUG
/*

134
sys/arch/i386/isa/fd.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: fd.c,v 1.96 1996/10/13 03:19:59 christos Exp $ */
/* $NetBSD: fd.c,v 1.97 1996/10/21 22:27:40 thorpej Exp $ */
/*-
* Copyright (c) 1993, 1994, 1995, 1996
@ -96,8 +96,8 @@ struct fdc_softc {
struct isadev sc_id;
void *sc_ih;
bus_chipset_tag_t sc_bc; /* ISA chipset identifier */
bus_io_handle_t sc_ioh; /* ISA io handle */
bus_space_tag_t sc_iot; /* ISA i/o space identifier */
bus_space_handle_t sc_ioh; /* ISA io handle */
int sc_drq;
@ -207,7 +207,7 @@ void fd_set_motor __P((struct fdc_softc *fdc, int reset));
void fd_motor_off __P((void *arg));
void fd_motor_on __P((void *arg));
int fdcresult __P((struct fdc_softc *fdc));
int out_fdc __P((bus_chipset_tag_t bc, bus_io_handle_t ioh, u_char x));
int out_fdc __P((bus_space_tag_t iot, bus_space_handle_t ioh, u_char x));
void fdcstart __P((struct fdc_softc *fdc));
void fdcstatus __P((struct device *dv, int n, char *s));
void fdctimeout __P((void *arg));
@ -223,27 +223,27 @@ fdcprobe(parent, match, aux)
void *match, *aux;
{
register struct isa_attach_args *ia = aux;
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
bus_space_tag_t iot;
bus_space_handle_t ioh;
int rv;
bc = ia->ia_bc;
iot = ia->ia_iot;
rv = 0;
/* Map the i/o space. */
if (bus_io_map(bc, ia->ia_iobase, FDC_NPORT, &ioh))
if (bus_space_map(iot, ia->ia_iobase, FDC_NPORT, 0, &ioh))
return 0;
/* reset */
bus_io_write_1(bc, ioh, fdout, 0);
bus_space_write_2(iot, ioh, fdout, 0);
delay(100);
bus_io_write_1(bc, ioh, fdout, FDO_FRST);
bus_space_write_2(iot, ioh, fdout, FDO_FRST);
/* see if it can handle a command */
if (out_fdc(bc, ioh, NE7CMD_SPECIFY) < 0)
if (out_fdc(iot, ioh, NE7CMD_SPECIFY) < 0)
goto out;
out_fdc(bc, ioh, 0xdf);
out_fdc(bc, ioh, 2);
out_fdc(iot, ioh, 0xdf);
out_fdc(iot, ioh, 2);
#ifdef NEWCONFIG
if (ia->ia_iobase == IOBASEUNK || ia->ia_drq == DRQUNK)
@ -255,9 +255,9 @@ fdcprobe(parent, match, aux)
goto out;
/* reset it again */
bus_io_write_1(bc, ioh, fdout, 0);
bus_space_write_2(iot, ioh, fdout, 0);
delay(100);
bus_io_write_1(bc, ioh, fdout, FDO_FRST);
bus_space_write_2(iot, ioh, fdout, FDO_FRST);
}
#endif
@ -266,7 +266,7 @@ fdcprobe(parent, match, aux)
ia->ia_msize = 0;
out:
bus_io_unmap(bc, ioh, FDC_NPORT);
bus_space_unmap(iot, ioh, FDC_NPORT);
return rv;
}
@ -284,9 +284,9 @@ fdcforceintr(aux)
/* the motor is off; this should generate an error with or
without a disk drive present */
out_fdc(bc, ioh, NE7CMD_SEEK);
out_fdc(bc, ioh, 0);
out_fdc(bc, ioh, 0);
out_fdc(iot, ioh, NE7CMD_SEEK);
out_fdc(iot, ioh, 0);
out_fdc(iot, ioh, 0);
}
#endif
@ -323,19 +323,19 @@ fdcattach(parent, self, aux)
void *aux;
{
struct fdc_softc *fdc = (void *)self;
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
bus_space_tag_t iot;
bus_space_handle_t ioh;
struct isa_attach_args *ia = aux;
struct fdc_attach_args fa;
int type;
bc = ia->ia_bc;
iot = ia->ia_iot;
/* Re-map the I/O space. */
if (bus_io_map(bc, ia->ia_iobase, FDC_NPORT, &ioh))
if (bus_space_map(iot, ia->ia_iobase, FDC_NPORT, 0, &ioh))
panic("fdcattach: couldn't map I/O ports");
fdc->sc_bc = bc;
fdc->sc_iot = iot;
fdc->sc_ioh = ioh;
fdc->sc_drq = ia->ia_drq;
@ -380,8 +380,8 @@ fdprobe(parent, match, aux)
struct cfdata *cf = match;
struct fdc_attach_args *fa = aux;
int drive = fa->fa_drive;
bus_chipset_tag_t bc = fdc->sc_bc;
bus_io_handle_t ioh = fdc->sc_ioh;
bus_space_tag_t iot = fdc->sc_iot;
bus_space_handle_t ioh = fdc->sc_ioh;
int n;
if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != drive)
@ -395,14 +395,14 @@ fdprobe(parent, match, aux)
return 0;
/* select drive and turn on motor */
bus_io_write_1(bc, ioh, fdout, drive | FDO_FRST | FDO_MOEN(drive));
bus_space_write_2(iot, ioh, fdout, drive | FDO_FRST | FDO_MOEN(drive));
/* wait for motor to spin up */
delay(250000);
out_fdc(bc, ioh, NE7CMD_RECAL);
out_fdc(bc, ioh, drive);
out_fdc(iot, ioh, NE7CMD_RECAL);
out_fdc(iot, ioh, drive);
/* wait for recalibrate */
delay(2000000);
out_fdc(bc, ioh, NE7CMD_SENSEI);
out_fdc(iot, ioh, NE7CMD_SENSEI);
n = fdcresult(fdc);
#ifdef FD_DEBUG
{
@ -414,7 +414,7 @@ fdprobe(parent, match, aux)
}
#endif
/* turn off motor */
bus_io_write_1(bc, ioh, fdout, FDO_FRST);
bus_space_write_1(iot, ioh, fdout, FDO_FRST);
if (n != 2 || (fdc->sc_status[0] & 0xf8) != 0x20)
return 0;
@ -663,7 +663,7 @@ fd_set_motor(fdc, reset)
for (n = 0; n < 4; n++)
if ((fd = fdc->sc_fd[n]) && (fd->sc_flags & FD_MOTOR))
status |= FDO_MOEN(n);
bus_io_write_1(fdc->sc_bc, fdc->sc_ioh, fdout, status);
bus_space_write_2(fdc->sc_iot, fdc->sc_ioh, fdout, status);
}
void
@ -698,14 +698,14 @@ int
fdcresult(fdc)
struct fdc_softc *fdc;
{
bus_chipset_tag_t bc = fdc->sc_bc;
bus_io_handle_t ioh = fdc->sc_ioh;
bus_space_tag_t iot = fdc->sc_iot;
bus_space_handle_t ioh = fdc->sc_ioh;
u_char i;
int j = 100000,
n = 0;
for (; j; j--) {
i = bus_io_read_1(bc, ioh, fdsts) &
i = bus_space_read_1(iot, ioh, fdsts) &
(NE7_DIO | NE7_RQM | NE7_CB);
if (i == NE7_RQM)
return n;
@ -714,7 +714,7 @@ fdcresult(fdc)
log(LOG_ERR, "fdcresult: overrun\n");
return -1;
}
fdc->sc_status[n++] = bus_io_read_1(bc, ioh, fddata);
fdc->sc_status[n++] = bus_space_read_1(iot, ioh, fddata);
}
}
log(LOG_ERR, "fdcresult: timeout\n");
@ -722,20 +722,20 @@ fdcresult(fdc)
}
int
out_fdc(bc, ioh, x)
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
out_fdc(iot, ioh, x)
bus_space_tag_t iot;
bus_space_handle_t ioh;
u_char x;
{
int i = 100000;
while ((bus_io_read_1(bc, ioh, fdsts) & NE7_DIO) && i-- > 0);
while ((bus_space_read_1(iot, ioh, fdsts) & NE7_DIO) && i-- > 0);
if (i <= 0)
return -1;
while ((bus_io_read_1(bc, ioh, fdsts) & NE7_RQM) == 0 && i-- > 0);
while ((bus_space_read_1(iot, ioh, fdsts) & NE7_RQM) == 0 && i-- > 0);
if (i <= 0)
return -1;
bus_io_write_1(bc, ioh, fddata, x);
bus_space_write_2(iot, ioh, fddata, x);
return 0;
}
@ -809,7 +809,7 @@ fdcstatus(dv, n, s)
struct fdc_softc *fdc = (void *)dv->dv_parent;
if (n == 0) {
out_fdc(fdc->sc_bc, fdc->sc_ioh, NE7CMD_SENSEI);
out_fdc(fdc->sc_iot, fdc->sc_ioh, NE7CMD_SENSEI);
(void) fdcresult(fdc);
n = 2;
}
@ -881,8 +881,8 @@ fdcintr(arg)
#define cyl fdc->sc_status[1]
struct fd_softc *fd;
struct buf *bp;
bus_chipset_tag_t bc = fdc->sc_bc;
bus_io_handle_t ioh = fdc->sc_ioh;
bus_space_tag_t iot = fdc->sc_iot;
bus_space_handle_t ioh = fdc->sc_ioh;
int read, head, sec, i, nblks;
struct fd_type *type;
@ -937,13 +937,13 @@ loop:
if (fd->sc_cylin == bp->b_cylin)
goto doio;
out_fdc(bc, ioh, NE7CMD_SPECIFY);/* specify command */
out_fdc(bc, ioh, fd->sc_type->steprate);
out_fdc(bc, ioh, 6); /* XXX head load time == 6ms */
out_fdc(iot, ioh, NE7CMD_SPECIFY);/* specify command */
out_fdc(iot, ioh, fd->sc_type->steprate);
out_fdc(iot, ioh, 6); /* XXX head load time == 6ms */
out_fdc(bc, ioh, NE7CMD_SEEK); /* seek function */
out_fdc(bc, ioh, fd->sc_drive); /* drive number */
out_fdc(bc, ioh, bp->b_cylin * fd->sc_type->step);
out_fdc(iot, ioh, NE7CMD_SEEK); /* seek function */
out_fdc(iot, ioh, fd->sc_drive); /* drive number */
out_fdc(iot, ioh, bp->b_cylin * fd->sc_type->step);
fd->sc_cylin = -1;
fdc->sc_state = SEEKWAIT;
@ -983,24 +983,24 @@ loop:
isa_dmastart(read, bp->b_data + fd->sc_skip, fd->sc_nbytes,
fdc->sc_drq);
#endif
bus_io_write_1(bc, ioh, fdctl, type->rate);
bus_space_write_2(iot, ioh, fdctl, type->rate);
#ifdef FD_DEBUG
printf("fdcintr: %s drive %d track %d head %d sec %d nblks %d\n",
read ? "read" : "write", fd->sc_drive, fd->sc_cylin, head,
sec, nblks);
#endif
if (read)
out_fdc(bc, ioh, NE7CMD_READ); /* READ */
out_fdc(iot, ioh, NE7CMD_READ); /* READ */
else
out_fdc(bc, ioh, NE7CMD_WRITE); /* WRITE */
out_fdc(bc, ioh, (head << 2) | fd->sc_drive);
out_fdc(bc, ioh, fd->sc_cylin); /* track */
out_fdc(bc, ioh, head);
out_fdc(bc, ioh, sec + 1); /* sector +1 */
out_fdc(bc, ioh, type->secsize); /* sector size */
out_fdc(bc, ioh, type->sectrac); /* sectors/track */
out_fdc(bc, ioh, type->gap1); /* gap1 size */
out_fdc(bc, ioh, type->datalen); /* data length */
out_fdc(iot, ioh, NE7CMD_WRITE); /* WRITE */
out_fdc(iot, ioh, (head << 2) | fd->sc_drive);
out_fdc(iot, ioh, fd->sc_cylin); /* track */
out_fdc(iot, ioh, head);
out_fdc(iot, ioh, sec + 1); /* sector +1 */
out_fdc(iot, ioh, type->secsize); /* sector size */
out_fdc(iot, ioh, type->sectrac); /* sectors/track */
out_fdc(iot, ioh, type->gap1); /* gap1 size */
out_fdc(iot, ioh, type->datalen); /* data length */
fdc->sc_state = IOCOMPLETE;
disk_busy(&fd->sc_dk);
@ -1020,7 +1020,7 @@ loop:
disk_unbusy(&fd->sc_dk, 0); /* no data on seek */
/* Make sure seek really happened. */
out_fdc(bc, ioh, NE7CMD_SENSEI);
out_fdc(iot, ioh, NE7CMD_SENSEI);
if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 ||
cyl != bp->b_cylin * fd->sc_type->step) {
#ifdef FD_DEBUG
@ -1100,14 +1100,14 @@ loop:
untimeout(fdctimeout, fdc);
/* clear the controller output buffer */
for (i = 0; i < 4; i++) {
out_fdc(bc, ioh, NE7CMD_SENSEI);
out_fdc(iot, ioh, NE7CMD_SENSEI);
(void) fdcresult(fdc);
}
/* fall through */
case DORECAL:
out_fdc(bc, ioh, NE7CMD_RECAL); /* recalibrate function */
out_fdc(bc, ioh, fd->sc_drive);
out_fdc(iot, ioh, NE7CMD_RECAL); /* recalibrate function */
out_fdc(iot, ioh, fd->sc_drive);
fdc->sc_state = RECALWAIT;
timeout(fdctimeout, fdc, 5 * hz);
return 1; /* will return later */
@ -1120,7 +1120,7 @@ loop:
return 1; /* will return later */
case RECALCOMPLETE:
out_fdc(bc, ioh, NE7CMD_SENSEI);
out_fdc(iot, ioh, NE7CMD_SENSEI);
if (fdcresult(fdc) != 2 || (st0 & 0xf8) != 0x20 || cyl != 0) {
#ifdef FD_DEBUG
fdcstatus(&fd->sc_dev, 2, "recalibrate failed");

57
sys/arch/i386/isa/lms.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: lms.c,v 1.29 1996/10/13 03:20:02 christos Exp $ */
/* $NetBSD: lms.c,v 1.30 1996/10/21 22:27:41 thorpej Exp $ */
/*-
* Copyright (c) 1993, 1994 Charles Hannum.
@ -59,8 +59,8 @@ struct lms_softc { /* driver status information */
struct device sc_dev;
void *sc_ih;
bus_chipset_tag_t sc_bc; /* bus chipset identifier */
bus_io_handle_t sc_ioh; /* bus i/o handle */
bus_space_tag_t sc_iot; /* bus i/o space identifier */
bus_space_handle_t sc_ioh; /* bus i/o handle */
struct clist sc_q;
struct selinfo sc_rsel;
@ -91,37 +91,37 @@ lmsprobe(parent, match, aux)
void *match, *aux;
{
struct isa_attach_args *ia = aux;
bus_chipset_tag_t bc = ia->ia_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ia->ia_iot;
bus_space_handle_t ioh;
int rv;
/* Map the i/o space. */
if (bus_io_map(bc, ia->ia_iobase, LMS_NPORTS, &ioh))
if (bus_space_map(iot, ia->ia_iobase, LMS_NPORTS, 0, &ioh))
return 0;
rv = 0;
/* Configure and check for port present. */
bus_io_write_1(bc, ioh, LMS_CONFIG, 0x91);
bus_space_write_1(iot, ioh, LMS_CONFIG, 0x91);
delay(10);
bus_io_write_1(bc, ioh, LMS_SIGN, 0x0c);
bus_space_write_1(iot, ioh, LMS_SIGN, 0x0c);
delay(10);
if (bus_io_read_1(bc, ioh, LMS_SIGN) != 0x0c)
if (bus_space_read_1(iot, ioh, LMS_SIGN) != 0x0c)
goto out;
bus_io_write_1(bc, ioh, LMS_SIGN, 0x50);
bus_space_write_1(iot, ioh, LMS_SIGN, 0x50);
delay(10);
if (bus_io_read_1(bc, ioh, LMS_SIGN) != 0x50)
if (bus_space_read_1(iot, ioh, LMS_SIGN) != 0x50)
goto out;
/* Disable interrupts. */
bus_io_write_1(bc, ioh, LMS_CNTRL, 0x10);
bus_space_write_1(iot, ioh, LMS_CNTRL, 0x10);
rv = 1;
ia->ia_iosize = LMS_NPORTS;
ia->ia_msize = 0;
out:
bus_io_unmap(bc, ioh, LMS_NPORTS);
bus_space_unmap(iot, ioh, LMS_NPORTS);
return rv;
}
@ -136,8 +136,9 @@ lmsattach(parent, self, aux)
printf("\n");
/* Other initialization was done by lmsprobe. */
sc->sc_bc = ia->ia_bc;
if (bus_io_map(sc->sc_bc, ia->ia_iobase, LMS_NPORTS, &sc->sc_ioh))
sc->sc_iot = ia->ia_iot;
if (bus_space_map(sc->sc_iot, ia->ia_iobase, LMS_NPORTS, 0,
&sc->sc_ioh))
panic("lmsattach: couldn't map I/O ports");
sc->sc_state = 0;
@ -173,7 +174,7 @@ lmsopen(dev, flag, mode, p)
sc->sc_x = sc->sc_y = 0;
/* Enable interrupts. */
bus_io_write_1(sc->sc_bc, sc->sc_ioh, LMS_CNTRL, 0);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMS_CNTRL, 0);
return 0;
}
@ -188,7 +189,7 @@ lmsclose(dev, flag, mode, p)
struct lms_softc *sc = lms_cd.cd_devs[LMSUNIT(dev)];
/* Disable interrupts. */
bus_io_write_1(sc->sc_bc, sc->sc_ioh, LMS_CNTRL, 0x10);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LMS_CNTRL, 0x10);
sc->sc_state &= ~LMS_OPEN;
@ -303,8 +304,8 @@ lmsintr(arg)
void *arg;
{
struct lms_softc *sc = arg;
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
u_char hi, lo, buttons, changed;
char dx, dy;
u_char buffer[5];
@ -313,22 +314,22 @@ lmsintr(arg)
/* Interrupts are not expected. */
return 0;
bus_io_write_1(bc, ioh, LMS_CNTRL, 0xab);
hi = bus_io_read_1(bc, ioh, LMS_DATA);
bus_io_write_1(bc, ioh, LMS_CNTRL, 0x90);
lo = bus_io_read_1(bc, ioh, LMS_DATA);
bus_space_write_1(iot, ioh, LMS_CNTRL, 0xab);
hi = bus_space_read_1(iot, ioh, LMS_DATA);
bus_space_write_1(iot, ioh, LMS_CNTRL, 0x90);
lo = bus_space_read_1(iot, ioh, LMS_DATA);
dx = ((hi & 0x0f) << 4) | (lo & 0x0f);
/* Bounding at -127 avoids a bug in XFree86. */
dx = (dx == -128) ? -127 : dx;
bus_io_write_1(bc, ioh, LMS_CNTRL, 0xf0);
hi = bus_io_read_1(bc, ioh, LMS_DATA);
bus_io_write_1(bc, ioh, LMS_CNTRL, 0xd0);
lo = bus_io_read_1(bc, ioh, LMS_DATA);
bus_space_write_1(iot, ioh, LMS_CNTRL, 0xf0);
hi = bus_space_read_1(iot, ioh, LMS_DATA);
bus_space_write_1(iot, ioh, LMS_CNTRL, 0xd0);
lo = bus_space_read_1(iot, ioh, LMS_DATA);
dy = ((hi & 0x0f) << 4) | (lo & 0x0f);
dy = (dy == -128) ? 127 : -dy;
bus_io_write_1(bc, ioh, LMS_CNTRL, 0);
bus_space_write_1(iot, ioh, LMS_CNTRL, 0);
buttons = (~hi >> 5) & 0x07;
changed = ((buttons ^ sc->sc_status) & 0x07) << 3;

19
sys/arch/i386/pci/pci_compat.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pci_compat.c,v 1.3 1996/10/13 03:20:23 christos Exp $ */
/* $NetBSD: pci_compat.c,v 1.4 1996/10/21 22:28:54 thorpej Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@ -88,13 +88,13 @@ pci_map_io(tag, reg, iobasep)
int reg;
int *iobasep;
{
bus_io_addr_t ioaddr;
bus_io_size_t iosize;
bus_io_handle_t ioh;
bus_addr_t ioaddr;
bus_size_t iosize;
bus_space_handle_t ioh;
if (pci_io_find(NULL, tag, reg, &ioaddr, &iosize))
return (1);
if (bus_io_map(NULL, ioaddr, iosize, &ioh))
if (bus_space_map(I386_BUS_SPACE_IO, ioaddr, iosize, 0, &ioh))
return (1);
*iobasep = ioh;
@ -111,14 +111,15 @@ pci_map_mem(tag, reg, vap, pap)
int reg;
vm_offset_t *vap, *pap;
{
bus_mem_addr_t memaddr;
bus_mem_size_t memsize;
bus_mem_handle_t memh;
bus_addr_t memaddr;
bus_size_t memsize;
bus_space_handle_t memh;
int cacheable;
if (pci_mem_find(NULL, tag, reg, &memaddr, &memsize, &cacheable))
return (1);
if (bus_mem_map(NULL, memaddr, memsize, cacheable, &memh))
if (bus_space_map(I386_BUS_SPACE_MEM, memaddr, memsize,
cacheable, &memh))
return (1);
*vap = (vm_offset_t)memh;

100
sys/dev/eisa/ahb.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ahb.c,v 1.5 1996/10/13 01:37:09 christos Exp $ */
/* $NetBSD: ahb.c,v 1.6 1996/10/21 22:30:56 thorpej Exp $ */
#undef AHBDEBUG
#ifdef DDB
@ -87,9 +87,9 @@
struct ahb_softc {
struct device sc_dev;
bus_chipset_tag_t sc_bc;
bus_space_tag_t sc_iot;
bus_io_handle_t sc_ioh;
bus_space_handle_t sc_ioh;
int sc_irq;
void *sc_ih;
@ -108,7 +108,7 @@ void ahb_free_ecb __P((struct ahb_softc *, struct ahb_ecb *));
struct ahb_ecb *ahb_get_ecb __P((struct ahb_softc *, int));
struct ahb_ecb *ahb_ecb_phys_kv __P((struct ahb_softc *, physaddr));
void ahb_done __P((struct ahb_softc *, struct ahb_ecb *));
int ahb_find __P((bus_chipset_tag_t, bus_io_handle_t, struct ahb_softc *));
int ahb_find __P((bus_space_tag_t, bus_space_handle_t, struct ahb_softc *));
void ahb_init __P((struct ahb_softc *));
void ahbminphys __P((struct buf *));
int ahb_scsi_cmd __P((struct scsi_xfer *));
@ -157,8 +157,8 @@ ahbmatch(parent, match, aux)
void *match, *aux;
{
struct eisa_attach_args *ea = aux;
bus_chipset_tag_t bc = ea->ea_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ea->ea_iot;
bus_space_handle_t ioh;
int rv;
/* must match one of our known ID strings */
@ -168,12 +168,13 @@ ahbmatch(parent, match, aux)
strcmp(ea->ea_idstring, "ADP0400"))
return (0);
if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &ioh))
if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot),
EISA_SLOT_SIZE, 0, &ioh))
return (0);
rv = !ahb_find(bc, ioh, NULL);
rv = !ahb_find(iot, ioh, NULL);
bus_io_unmap(bc, ioh, EISA_SLOT_SIZE);
bus_space_unmap(iot, ioh, EISA_SLOT_SIZE);
return (rv);
}
@ -188,8 +189,8 @@ ahbattach(parent, self, aux)
{
struct eisa_attach_args *ea = aux;
struct ahb_softc *sc = (void *)self;
bus_chipset_tag_t bc = ea->ea_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ea->ea_iot;
bus_space_handle_t ioh;
eisa_chipset_tag_t ec = ea->ea_ec;
eisa_intr_handle_t ih;
const char *model, *intrstr;
@ -206,12 +207,13 @@ ahbattach(parent, self, aux)
model = "unknown model!";
printf(": %s\n", model);
if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &ioh))
if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot),
EISA_SLOT_SIZE, 0, &ioh))
panic("ahbattach: could not map I/O addresses");
sc->sc_bc = bc;
sc->sc_iot = iot;
sc->sc_ioh = ioh;
if (ahb_find(bc, ioh, sc))
if (ahb_find(iot, ioh, sc))
panic("ahbattach: ahb_find failed!");
ahb_init(sc);
@ -262,12 +264,12 @@ ahb_send_mbox(sc, opcode, ecb)
int opcode;
struct ahb_ecb *ecb;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int wait = 300; /* 1ms should be enough */
while (--wait) {
if ((bus_io_read_1(bc, ioh, G2STAT) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
if ((bus_space_read_1(iot, ioh, G2STAT) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
== (G2STAT_MBOX_EMPTY))
break;
delay(10);
@ -277,8 +279,8 @@ ahb_send_mbox(sc, opcode, ecb)
Debugger();
}
bus_io_write_4(bc, ioh, MBOXOUT0, KVTOPHYS(ecb)); /* don't know this will work */
bus_io_write_1(bc, ioh, ATTN, opcode | ecb->xs->sc_link->target);
bus_space_write_4(iot, ioh, MBOXOUT0, KVTOPHYS(ecb)); /* don't know this will work */
bus_space_write_1(iot, ioh, ATTN, opcode | ecb->xs->sc_link->target);
if ((ecb->xs->flags & SCSI_POLL) == 0)
timeout(ahb_timeout, ecb, (ecb->timeout * hz) / 1000);
@ -293,12 +295,12 @@ ahb_send_immed(sc, cmd, ecb)
u_long cmd;
struct ahb_ecb *ecb;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int wait = 100; /* 1 ms enough? */
while (--wait) {
if ((bus_io_read_1(bc, ioh, G2STAT) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
if ((bus_space_read_1(iot, ioh, G2STAT) & (G2STAT_BUSY | G2STAT_MBOX_EMPTY))
== (G2STAT_MBOX_EMPTY))
break;
delay(10);
@ -308,9 +310,9 @@ ahb_send_immed(sc, cmd, ecb)
Debugger();
}
bus_io_write_4(bc, ioh, MBOXOUT0, cmd); /* don't know this will work */
bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_SET_HOST_READY);
bus_io_write_1(bc, ioh, ATTN, OP_IMMED | ecb->xs->sc_link->target);
bus_space_write_4(iot, ioh, MBOXOUT0, cmd); /* don't know this will work */
bus_space_write_1(iot, ioh, G2CNTRL, G2CNTRL_SET_HOST_READY);
bus_space_write_1(iot, ioh, ATTN, OP_IMMED | ecb->xs->sc_link->target);
if ((ecb->xs->flags & SCSI_POLL) == 0)
timeout(ahb_timeout, ecb, (ecb->timeout * hz) / 1000);
@ -324,8 +326,8 @@ ahbintr(arg)
void *arg;
{
struct ahb_softc *sc = arg;
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct ahb_ecb *ecb;
u_char ahbstat;
u_long mboxval;
@ -334,7 +336,7 @@ ahbintr(arg)
printf("%s: ahbintr ", sc->sc_dev.dv_xname);
#endif /* AHBDEBUG */
if ((bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND) == 0)
if ((bus_space_read_1(iot, ioh, G2STAT) & G2STAT_INT_PEND) == 0)
return 0;
for (;;) {
@ -342,9 +344,9 @@ ahbintr(arg)
* First get all the information and then
* acknowlege the interrupt
*/
ahbstat = bus_io_read_1(bc, ioh, G2INTST);
mboxval = bus_io_read_4(bc, ioh, MBOXIN0);
bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
ahbstat = bus_space_read_1(iot, ioh, G2INTST);
mboxval = bus_space_read_4(iot, ioh, MBOXIN0);
bus_space_write_1(iot, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
#ifdef AHBDEBUG
printf("status = 0x%x ", ahbstat);
@ -386,7 +388,7 @@ ahbintr(arg)
ahb_done(sc, ecb);
next:
if ((bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND) == 0)
if ((bus_space_read_1(iot, ioh, G2STAT) & G2STAT_INT_PEND) == 0)
return 1;
}
}
@ -580,16 +582,16 @@ done:
* Start the board, ready for normal operation
*/
int
ahb_find(bc, ioh, sc)
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
ahb_find(iot, ioh, sc)
bus_space_tag_t iot;
bus_space_handle_t ioh;
struct ahb_softc *sc;
{
u_char intdef;
int i, irq, busid;
int wait = 1000; /* 1 sec enough? */
bus_io_write_1(bc, ioh, PORTADDR, PORTADDR_ENHANCED);
bus_space_write_1(iot, ioh, PORTADDR, PORTADDR_ENHANCED);
#define NO_NO 1
#ifdef NO_NO
@ -597,12 +599,12 @@ ahb_find(bc, ioh, sc)
* reset board, If it doesn't respond, assume
* that it's not there.. good for the probe
*/
bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_HARD_RESET);
bus_space_write_1(iot, ioh, G2CNTRL, G2CNTRL_HARD_RESET);
delay(1000);
bus_io_write_1(bc, ioh, G2CNTRL, 0);
bus_space_write_1(iot, ioh, G2CNTRL, 0);
delay(10000);
while (--wait) {
if ((bus_io_read_1(bc, ioh, G2STAT) & G2STAT_BUSY) == 0)
if ((bus_space_read_1(iot, ioh, G2STAT) & G2STAT_BUSY) == 0)
break;
delay(1000);
}
@ -612,23 +614,23 @@ ahb_find(bc, ioh, sc)
#endif /* AHBDEBUG */
return ENXIO;
}
i = bus_io_read_1(bc, ioh, MBOXIN0);
i = bus_space_read_1(iot, ioh, MBOXIN0);
if (i) {
printf("self test failed, val = 0x%x\n", i);
return EIO;
}
/* Set it again, just to be sure. */
bus_io_write_1(bc, ioh, PORTADDR, PORTADDR_ENHANCED);
bus_space_write_1(iot, ioh, PORTADDR, PORTADDR_ENHANCED);
#endif
while (bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND) {
while (bus_space_read_1(iot, ioh, G2STAT) & G2STAT_INT_PEND) {
printf(".");
bus_io_write_1(bc, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
bus_space_write_1(iot, ioh, G2CNTRL, G2CNTRL_CLEAR_EISA_INT);
delay(10000);
}
intdef = bus_io_read_1(bc, ioh, INTDEF);
intdef = bus_space_read_1(iot, ioh, INTDEF);
switch (intdef & 0x07) {
case INT9:
irq = 9;
@ -653,10 +655,10 @@ ahb_find(bc, ioh, sc)
return EIO;
}
bus_io_write_1(bc, ioh, INTDEF, (intdef | INTEN)); /* make sure we can interrupt */
bus_space_write_1(iot, ioh, INTDEF, (intdef | INTEN)); /* make sure we can interrupt */
/* who are we on the scsi bus? */
busid = (bus_io_read_1(bc, ioh, SCSIDEF) & HSCSIID);
busid = (bus_space_read_1(iot, ioh, SCSIDEF) & HSCSIID);
/* if we want to fill in softc, do so now */
if (sc != NULL) {
@ -884,15 +886,15 @@ ahb_poll(sc, xs, count)
struct scsi_xfer *xs;
int count;
{ /* in msec */
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
while (count) {
/*
* If we had interrupts enabled, would we
* have got an interrupt?
*/
if (bus_io_read_1(bc, ioh, G2STAT) & G2STAT_INT_PEND)
if (bus_space_read_1(iot, ioh, G2STAT) & G2STAT_INT_PEND)
ahbintr(sc);
if (xs->flags & ITSDONE)
return 0;

38
sys/dev/eisa/ahc_eisa.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ahc_eisa.c,v 1.9 1996/10/13 01:37:10 christos Exp $ */
/* $NetBSD: ahc_eisa.c,v 1.10 1996/10/21 22:30:58 thorpej Exp $ */
/*
* Product specific probe and attach routines for:
@ -199,7 +199,7 @@ aic7770probe(void)
#define bootverbose 0
#endif
int ahc_eisa_irq __P((bus_chipset_tag_t, bus_io_handle_t));
int ahc_eisa_irq __P((bus_space_tag_t, bus_space_handle_t));
int ahc_eisa_match __P((struct device *, void *, void *));
void ahc_eisa_attach __P((struct device *, struct device *, void *));
@ -212,15 +212,15 @@ struct cfattach ahc_eisa_ca = {
* Return irq setting of the board, otherwise -1.
*/
int
ahc_eisa_irq(bc, ioh)
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
ahc_eisa_irq(iot, ioh)
bus_space_tag_t iot;
bus_space_handle_t ioh;
{
int irq;
u_char intdef;
ahc_reset("ahc_eisa", bc, ioh);
intdef = bus_io_read_1(bc, ioh, INTDEF);
ahc_reset("ahc_eisa", iot, ioh);
intdef = bus_space_read_1(iot, ioh, INTDEF);
switch (irq = (intdef & 0xf)) {
case 9:
case 10:
@ -249,8 +249,8 @@ ahc_eisa_match(parent, match, aux)
void *match, *aux;
{
struct eisa_attach_args *ea = aux;
bus_chipset_tag_t bc = ea->ea_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ea->ea_iot;
bus_space_handle_t ioh;
int irq;
/* must match one of our known ID strings */
@ -263,13 +263,13 @@ ahc_eisa_match(parent, match, aux)
)
return (0);
if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + AHC_EISA_SLOT_OFFSET,
AHC_EISA_IOSIZE, &ioh))
if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
AHC_EISA_SLOT_OFFSET, AHC_EISA_IOSIZE, 0, &ioh))
return (0);
irq = ahc_eisa_irq(bc, ioh);
irq = ahc_eisa_irq(iot, ioh);
bus_io_unmap(bc, ioh, AHC_EISA_IOSIZE);
bus_space_unmap(iot, ioh, AHC_EISA_IOSIZE);
return (irq >= 0);
}
@ -341,17 +341,17 @@ ahc_eisa_attach(parent, self, aux)
struct ahc_data *ahc = (void *)self;
struct eisa_attach_args *ea = aux;
bus_chipset_tag_t bc = ea->ea_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ea->ea_iot;
bus_space_handle_t ioh;
int irq;
eisa_chipset_tag_t ec = ea->ea_ec;
eisa_intr_handle_t ih;
const char *model, *intrstr;
if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + AHC_EISA_SLOT_OFFSET,
AHC_EISA_IOSIZE, &ioh))
if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
AHC_EISA_SLOT_OFFSET, AHC_EISA_IOSIZE, 0, &ioh))
panic("ahc_eisa_attach: could not map I/O addresses");
if ((irq = ahc_eisa_irq(bc, ioh)) < 0)
if ((irq = ahc_eisa_irq(iot, ioh)) < 0)
panic("ahc_eisa_attach: ahc_eisa_irq failed!");
if (strcmp(ea->ea_idstring, "ADP7770") == 0) {
@ -374,7 +374,7 @@ ahc_eisa_attach(parent, self, aux)
}
printf(": %s\n", model);
ahc_construct(ahc, bc, ioh, type, AHC_FNONE);
ahc_construct(ahc, iot, ioh, type, AHC_FNONE);
if (eisa_intr_map(ec, irq, &ih)) {
printf("%s: couldn't map interrupt (%d)\n",
ahc->sc_dev.dv_xname, irq);

26
sys/dev/eisa/bha_eisa.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bha_eisa.c,v 1.4 1996/10/13 01:37:11 christos Exp $ */
/* $NetBSD: bha_eisa.c,v 1.5 1996/10/21 22:31:00 thorpej Exp $ */
/*
* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
@ -67,8 +67,8 @@ bha_eisa_match(parent, match, aux)
void *match, *aux;
{
struct eisa_attach_args *ea = aux;
bus_chipset_tag_t bc = ea->ea_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ea->ea_iot;
bus_space_handle_t ioh;
int rv;
/* must match one of our known ID strings */
@ -76,13 +76,13 @@ bha_eisa_match(parent, match, aux)
strcmp(ea->ea_idstring, "BUS4202"))
return (0);
if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + BHA_EISA_SLOT_OFFSET,
BHA_EISA_IOSIZE, &ioh))
if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
BHA_EISA_SLOT_OFFSET, BHA_EISA_IOSIZE, 0, &ioh))
return (0);
rv = bha_find(bc, ioh, NULL);
rv = bha_find(iot, ioh, NULL);
bus_io_unmap(bc, ioh, BHA_EISA_IOSIZE);
bus_space_unmap(iot, ioh, BHA_EISA_IOSIZE);
return (rv);
}
@ -97,8 +97,8 @@ bha_eisa_attach(parent, self, aux)
{
struct eisa_attach_args *ea = aux;
struct bha_softc *sc = (void *)self;
bus_chipset_tag_t bc = ea->ea_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ea->ea_iot;
bus_space_handle_t ioh;
eisa_chipset_tag_t ec = ea->ea_ec;
eisa_intr_handle_t ih;
const char *model, *intrstr;
@ -111,13 +111,13 @@ bha_eisa_attach(parent, self, aux)
model = "unknown model!";
printf(": %s\n", model);
if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + BHA_EISA_SLOT_OFFSET,
BHA_EISA_IOSIZE, &ioh))
if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
BHA_EISA_SLOT_OFFSET, BHA_EISA_IOSIZE, 0, &ioh))
panic("bha_attach: could not map I/O addresses");
sc->sc_bc = bc;
sc->sc_iot = iot;
sc->sc_ioh = ioh;
if (!bha_find(bc, ioh, sc))
if (!bha_find(iot, ioh, sc))
panic("bha_attach: bha_find failed!");
if (eisa_intr_map(ec, sc->sc_irq, &ih)) {

24
sys/dev/eisa/eisa.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: eisa.c,v 1.14 1996/10/13 01:37:12 christos Exp $ */
/* $NetBSD: eisa.c,v 1.15 1996/10/21 22:31:01 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou
@ -115,14 +115,15 @@ eisaattach(parent, self, aux)
void *aux;
{
struct eisabus_attach_args *eba = aux;
bus_chipset_tag_t bc;
bus_space_tag_t iot, memt;
eisa_chipset_tag_t ec;
int slot, maxnslots;
eisa_attach_hook(parent, self, eba);
printf("\n");
bc = eba->eba_bc;
iot = eba->eba_iot;
memt = eba->eba_memt;
ec = eba->eba_ec;
/*
@ -135,10 +136,11 @@ eisaattach(parent, self, aux)
for (slot = 1; slot < maxnslots; slot++) {
struct eisa_attach_args ea;
u_int slotaddr;
bus_io_handle_t slotioh;
bus_space_handle_t slotioh;
int i;
ea.ea_bc = bc;
ea.ea_iot = iot;
ea.ea_memt = memt;
ea.ea_ec = ec;
ea.ea_slot = slot;
slotaddr = EISA_SLOT_ADDR(slot);
@ -148,7 +150,7 @@ eisaattach(parent, self, aux)
* space. If we can't, assume nothing's there but warn
* about it.
*/
if (bus_io_map(bc, slotaddr, EISA_SLOT_SIZE, &slotioh)) {
if (bus_space_map(iot, slotaddr, EISA_SLOT_SIZE, 0, &slotioh)) {
printf("%s: can't map I/O space for slot %d\n",
self->dv_xname, slot);
continue;
@ -156,7 +158,7 @@ eisaattach(parent, self, aux)
/* Get the vendor ID bytes */
for (i = 0; i < EISA_NVIDREGS; i++)
ea.ea_vid[i] = bus_io_read_1(bc, slotioh,
ea.ea_vid[i] = bus_space_read_1(iot, slotioh,
EISA_SLOTOFF_VID + i);
/* Check for device existence */
@ -167,7 +169,7 @@ eisaattach(parent, self, aux)
printf("\t(0x%x, 0x%x)\n", ea.ea_vid[0],
ea.ea_vid[1]);
#endif
bus_io_unmap(bc, slotioh, EISA_SLOT_SIZE);
bus_space_unmap(iot, slotioh, EISA_SLOT_SIZE);
continue;
}
@ -175,13 +177,13 @@ eisaattach(parent, self, aux)
if (EISA_VENDID_IDDELAY(ea.ea_vid)) {
printf("%s slot %d not configured by BIOS?\n",
self->dv_xname, slot);
bus_io_unmap(bc, slotioh, EISA_SLOT_SIZE);
bus_space_unmap(iot, slotioh, EISA_SLOT_SIZE);
continue;
}
/* Get the product ID bytes */
for (i = 0; i < EISA_NPIDREGS; i++)
ea.ea_pid[i] = bus_io_read_1(bc, slotioh,
ea.ea_pid[i] = bus_space_read_1(iot, slotioh,
EISA_SLOTOFF_PID + i);
/* Create the ID string from the vendor and product IDs */
@ -195,7 +197,7 @@ eisaattach(parent, self, aux)
ea.ea_idstring[7] = '\0'; /* sanity */
/* We no longer need the I/O handle; free it. */
bus_io_unmap(bc, slotioh, EISA_SLOT_SIZE);
bus_space_unmap(iot, slotioh, EISA_SLOT_SIZE);
/* Attach matching device. */
config_found_sm(self, &ea, eisaprint, eisasubmatch);

10
sys/dev/eisa/eisavar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: eisavar.h,v 1.9 1996/04/12 06:34:36 cgd Exp $ */
/* $NetBSD: eisavar.h,v 1.10 1996/10/21 22:31:03 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou
@ -69,8 +69,9 @@ typedef int eisa_slot_t; /* really only needs to be 4 bits */
* EISA bus attach arguments.
*/
struct eisabus_attach_args {
char *eba_busname; /* XXX should be common */
bus_chipset_tag_t eba_bc; /* XXX should be common */
char *eba_busname; /* XXX should be common */
bus_space_tag_t eba_iot; /* eisa i/o space tag */
bus_space_tag_t eba_memt; /* eisa mem space tag */
eisa_chipset_tag_t eba_ec;
};
@ -78,7 +79,8 @@ struct eisabus_attach_args {
* EISA device attach arguments.
*/
struct eisa_attach_args {
bus_chipset_tag_t ea_bc;
bus_space_tag_t ea_iot; /* eisa i/o space tag */
bus_space_tag_t ea_memt; /* eisa mem space tag */
eisa_chipset_tag_t ea_ec;
eisa_slot_t ea_slot;

21
sys/dev/eisa/if_ep_eisa.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_ep_eisa.c,v 1.8 1996/10/13 01:37:13 christos Exp $ */
/* $NetBSD: if_ep_eisa.c,v 1.9 1996/10/21 22:31:04 thorpej Exp $ */
/*
* Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
@ -112,8 +112,8 @@ ep_eisa_attach(parent, self, aux)
{
struct ep_softc *sc = (void *)self;
struct eisa_attach_args *ea = aux;
bus_chipset_tag_t bc = ea->ea_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ea->ea_iot;
bus_space_handle_t ioh;
u_int16_t k, conn = 0;
eisa_chipset_tag_t ec = ea->ea_ec;
eisa_intr_handle_t ih;
@ -121,29 +121,30 @@ ep_eisa_attach(parent, self, aux)
u_int irq;
/* Map i/o space. */
if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &ioh))
if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot),
EISA_SLOT_SIZE, 0, &ioh))
panic("ep_eisa_attach: can't map i/o space");
sc->bustype = EP_BUS_EISA;
sc->sc_ioh = ioh;
sc->sc_bc = bc;
sc->sc_iot = iot;
/* Reset card. */
bus_io_write_1(bc, ioh, EISA_CONTROL, EISA_ENABLE | EISA_RESET);
bus_space_write_1(iot, ioh, EISA_CONTROL, EISA_ENABLE | EISA_RESET);
delay(10);
bus_io_write_1(bc, ioh, EISA_CONTROL, EISA_ENABLE);
bus_space_write_1(iot, ioh, EISA_CONTROL, EISA_ENABLE);
/* Wait for reset? */
delay(1000);
/* XXX What is this doing?! Reading the i/o address? */
k = bus_io_read_2(bc, ioh, EP_W0_ADDRESS_CFG);
k = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG);
k = (k & 0x1f) * 0x10 + 0x200;
/* Read the IRQ from the card. */
irq = bus_io_read_2(bc, ioh, EP_W0_RESOURCE_CFG) >> 12;
irq = bus_space_read_2(iot, ioh, EP_W0_RESOURCE_CFG) >> 12;
GO_WINDOW(0);
conn = bus_io_read_2(bc, ioh, EP_W0_CONFIG_CTRL);
conn = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL);
if (strcmp(ea->ea_idstring, "TCM5091") == 0)
model = EISA_PRODUCT_TCM5091;

49
sys/dev/eisa/if_fea.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_fea.c,v 1.8 1996/10/13 01:37:14 christos Exp $ */
/* $NetBSD: if_fea.c,v 1.9 1996/10/21 22:31:05 thorpej Exp $ */
/*-
* Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
@ -156,22 +156,29 @@ pdq_eisa_devinit(
pdq_softc_t *sc)
{
pdq_uint8_t data;
pdq_bus_t tag;
#if defined(__NetBSD__)
tag = sc->sc_iotag;
#else
tag = sc->sc_bc;
#endif
/*
* Do the standard initialization for the DEFEA registers.
*/
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_FUNCTION_CTRL, 0x23);
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CMP_1_1, (sc->sc_iobase >> 8) & 0xF0);
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CMP_0_1, (sc->sc_iobase >> 8) & 0xF0);
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_SLOT_CTRL, 0x01);
data = PDQ_OS_IORD_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF);
PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_FUNCTION_CTRL, 0x23);
PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_IO_CMP_1_1, (sc->sc_iobase >> 8) & 0xF0);
PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_IO_CMP_0_1, (sc->sc_iobase >> 8) & 0xF0);
PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_SLOT_CTRL, 0x01);
data = PDQ_OS_IORD_8(tag, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF);
#if defined(PDQ_IOMAPPED)
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data & ~1);
PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data & ~1);
#else
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data | 1);
PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_BURST_HOLDOFF, data | 1);
#endif
data = PDQ_OS_IORD_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0);
PDQ_OS_IOWR_8(sc->sc_bc, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0, data | DEFEA_INTRENABLE);
data = PDQ_OS_IORD_8(tag, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0);
PDQ_OS_IOWR_8(tag, sc->sc_iobase, PDQ_EISA_IO_CONFIG_STAT_0, data | DEFEA_INTRENABLE);
}
#if defined(__FreeBSD__)
@ -462,27 +469,37 @@ pdq_eisa_attach(
eisa_intr_handle_t ih;
const char *intrstr;
sc->sc_bc = ea->ea_bc;
sc->sc_iotag = ea->ea_iot;
bcopy(sc->sc_dev.dv_xname, sc->sc_if.if_xname, IFNAMSIZ);
sc->sc_if.if_flags = 0;
sc->sc_if.if_softc = sc;
if (bus_io_map(sc->sc_bc, EISA_SLOT_ADDR(ea->ea_slot), EISA_SLOT_SIZE, &sc->sc_iobase)) {
/*
* NOTE: sc_bc is an alias for sc_csrtag and sc_membase is
* an alias for sc_csrhandle. sc_iobase is used here to
* check the card's configuration.
*/
if (bus_space_map(sc->sc_iotag, EISA_SLOT_ADDR(ea->ea_slot),
EISA_SLOT_SIZE, 0, &sc->sc_iobase)) {
printf("\n%s: failed to map I/O!\n", sc->sc_dev.dv_xname);
return;
}
pdq_eisa_subprobe(sc->sc_bc, sc->sc_iobase, &maddr, &msize, &irq);
pdq_eisa_subprobe(sc->sc_iotag, sc->sc_iobase, &maddr, &msize, &irq);
#if !defined(PDQ_IOMAPPED)
#if defined(PDQ_IOMAPPED)
sc->sc_csrtag = sc->sc_iotag;
sc->sc_csrhandle = sc->sc_iobase;
#else
if (maddr == 0 || msize == 0) {
printf("\n%s: error: memory not enabled! ECU reconfiguration required\n",
sc->sc_dev.dv_xname);
return;
}
if (bus_mem_map(sc->sc_bc, maddr, msize, 0, &sc->sc_membase)) {
bus_io_unmap(sc->sc_bc, sc->sc_iobase, EISA_SLOT_SIZE);
if (bus_space_map(sc->sc_csrtag, maddr, msize, 0, &sc->sc_csrhandle)) {
bus_space_unmap(sc->sc_iotag, sc->sc_iobase, EISA_SLOT_SIZE);
printf("\n%s: failed to map memory (0x%x-0x%x)!\n",
sc->sc_dev.dv_xname, maddr, maddr + msize - 1);
return;

96
sys/dev/eisa/uha_eisa.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: uha_eisa.c,v 1.4 1996/10/13 01:37:15 christos Exp $ */
/* $NetBSD: uha_eisa.c,v 1.5 1996/10/21 22:31:07 thorpej Exp $ */
/*
* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
@ -61,7 +61,7 @@ struct cfattach uha_eisa_ca = {
#define KVTOPHYS(x) vtophys(x)
int u24_find __P((bus_chipset_tag_t, bus_io_handle_t, struct uha_softc *));
int u24_find __P((bus_space_tag_t, bus_space_handle_t, struct uha_softc *));
void u24_start_mbox __P((struct uha_softc *, struct uha_mscp *));
int u24_poll __P((struct uha_softc *, struct scsi_xfer *, int));
int u24_intr __P((void *));
@ -78,21 +78,21 @@ uha_eisa_match(parent, match, aux)
void *match, *aux;
{
struct eisa_attach_args *ea = aux;
bus_chipset_tag_t bc = ea->ea_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ea->ea_iot;
bus_space_handle_t ioh;
int rv;
/* must match one of our known ID strings */
if (strncmp(ea->ea_idstring, "USC024", 6))
return (0);
if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + UHA_EISA_SLOT_OFFSET,
UHA_EISA_IOSIZE, &ioh))
if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
UHA_EISA_SLOT_OFFSET, UHA_EISA_IOSIZE, 0, &ioh))
return (0);
rv = u24_find(bc, ioh, NULL);
rv = u24_find(iot, ioh, NULL);
bus_io_unmap(bc, ioh, UHA_EISA_IOSIZE);
bus_space_unmap(iot, ioh, UHA_EISA_IOSIZE);
return (rv);
}
@ -107,8 +107,8 @@ uha_eisa_attach(parent, self, aux)
{
struct eisa_attach_args *ea = aux;
struct uha_softc *sc = (void *)self;
bus_chipset_tag_t bc = ea->ea_bc;
bus_io_handle_t ioh;
bus_space_tag_t iot = ea->ea_iot;
bus_space_handle_t ioh;
eisa_chipset_tag_t ec = ea->ea_ec;
eisa_intr_handle_t ih;
const char *model, *intrstr;
@ -119,13 +119,13 @@ uha_eisa_attach(parent, self, aux)
model = "unknown model!";
printf(": %s\n", model);
if (bus_io_map(bc, EISA_SLOT_ADDR(ea->ea_slot) + UHA_EISA_SLOT_OFFSET,
UHA_EISA_IOSIZE, &ioh))
if (bus_space_map(iot, EISA_SLOT_ADDR(ea->ea_slot) +
UHA_EISA_SLOT_OFFSET, UHA_EISA_IOSIZE, 0, &ioh))
panic("uha_attach: could not map I/O addresses");
sc->sc_bc = bc;
sc->sc_iot = iot;
sc->sc_ioh = ioh;
if (!u24_find(bc, ioh, sc))
if (!u24_find(iot, ioh, sc))
panic("uha_attach: u24_find failed!");
if (eisa_intr_map(ec, sc->sc_irq, &ih)) {
@ -155,18 +155,18 @@ uha_eisa_attach(parent, self, aux)
}
int
u24_find(bc, ioh, sc)
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
u24_find(iot, ioh, sc)
bus_space_tag_t iot;
bus_space_handle_t ioh;
struct uha_softc *sc;
{
u_int8_t config0, config1, config2;
int irq, drq;
int resetcount = 4000; /* 4 secs? */
config0 = bus_io_read_1(bc, ioh, U24_CONFIG + 0);
config1 = bus_io_read_1(bc, ioh, U24_CONFIG + 1);
config2 = bus_io_read_1(bc, ioh, U24_CONFIG + 2);
config0 = bus_space_read_1(iot, ioh, U24_CONFIG + 0);
config1 = bus_space_read_1(iot, ioh, U24_CONFIG + 1);
config2 = bus_space_read_1(iot, ioh, U24_CONFIG + 2);
if ((config0 & U24_MAGIC1) == 0 ||
(config1 & U24_MAGIC2) == 0)
return (0);
@ -192,10 +192,10 @@ u24_find(bc, ioh, sc)
return (0);
}
bus_io_write_1(bc, ioh, U24_LINT, UHA_ASRST);
bus_space_write_1(iot, ioh, U24_LINT, UHA_ASRST);
while (--resetcount) {
if (bus_io_read_1(bc, ioh, U24_LINT))
if (bus_space_read_1(iot, ioh, U24_LINT))
break;
delay(1000); /* 1 mSec per loop */
}
@ -219,12 +219,12 @@ u24_start_mbox(sc, mscp)
struct uha_softc *sc;
struct uha_mscp *mscp;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int spincount = 100000; /* 1s should be enough */
while (--spincount) {
if ((bus_io_read_1(bc, ioh, U24_LINT) & U24_LDIP) == 0)
if ((bus_space_read_1(iot, ioh, U24_LINT) & U24_LDIP) == 0)
break;
delay(100);
}
@ -234,12 +234,12 @@ u24_start_mbox(sc, mscp)
Debugger();
}
bus_io_write_4(bc, ioh, U24_OGMPTR, KVTOPHYS(mscp));
bus_space_write_4(iot, ioh, U24_OGMPTR, KVTOPHYS(mscp));
if (mscp->flags & MSCP_ABORT)
bus_io_write_1(bc, ioh, U24_OGMCMD, 0x80);
bus_space_write_1(iot, ioh, U24_OGMCMD, 0x80);
else
bus_io_write_1(bc, ioh, U24_OGMCMD, 0x01);
bus_io_write_1(bc, ioh, U24_LINT, U24_OGMFULL);
bus_space_write_1(iot, ioh, U24_OGMCMD, 0x01);
bus_space_write_1(iot, ioh, U24_LINT, U24_OGMFULL);
if ((mscp->xs->flags & SCSI_POLL) == 0)
timeout(uha_timeout, mscp, (mscp->timeout * hz) / 1000);
@ -251,15 +251,15 @@ u24_poll(sc, xs, count)
struct scsi_xfer *xs;
int count;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
while (count) {
/*
* If we had interrupts enabled, would we
* have got an interrupt?
*/
if (bus_io_read_1(bc, ioh, U24_SINT) & U24_SDIP)
if (bus_space_read_1(iot, ioh, U24_SINT) & U24_SDIP)
u24_intr(sc);
if (xs->flags & ITSDONE)
return (0);
@ -274,8 +274,8 @@ u24_intr(arg)
void *arg;
{
struct uha_softc *sc = arg;
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct uha_mscp *mscp;
u_char uhastat;
u_long mboxval;
@ -284,7 +284,7 @@ u24_intr(arg)
printf("%s: uhaintr ", sc->sc_dev.dv_xname);
#endif /*UHADEBUG */
if ((bus_io_read_1(bc, ioh, U24_SINT) & U24_SDIP) == 0)
if ((bus_space_read_1(iot, ioh, U24_SINT) & U24_SDIP) == 0)
return (0);
for (;;) {
@ -292,10 +292,10 @@ u24_intr(arg)
* First get all the information and then
* acknowledge the interrupt
*/
uhastat = bus_io_read_1(bc, ioh, U24_SINT);
mboxval = bus_io_read_4(bc, ioh, U24_ICMPTR);
bus_io_write_1(bc, ioh, U24_SINT, U24_ICM_ACK);
bus_io_write_1(bc, ioh, U24_ICMCMD, 0);
uhastat = bus_space_read_1(iot, ioh, U24_SINT);
mboxval = bus_space_read_4(iot, ioh, U24_ICMPTR);
bus_space_write_1(iot, ioh, U24_SINT, U24_ICM_ACK);
bus_space_write_1(iot, ioh, U24_ICMCMD, 0);
#ifdef UHADEBUG
printf("status = 0x%x ", uhastat);
@ -313,7 +313,7 @@ u24_intr(arg)
untimeout(uha_timeout, mscp);
uha_done(sc, mscp);
if ((bus_io_read_1(bc, ioh, U24_SINT) & U24_SDIP) == 0)
if ((bus_space_read_1(iot, ioh, U24_SINT) & U24_SDIP) == 0)
return (1);
}
}
@ -322,18 +322,18 @@ void
u24_init(sc)
struct uha_softc *sc;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
/* free OGM and ICM */
bus_io_write_1(bc, ioh, U24_OGMCMD, 0);
bus_io_write_1(bc, ioh, U24_ICMCMD, 0);
bus_space_write_1(iot, ioh, U24_OGMCMD, 0);
bus_space_write_1(iot, ioh, U24_ICMCMD, 0);
/* make sure interrupts are enabled */
#ifdef UHADEBUG
printf("u24_init: lmask=%02x, smask=%02x\n",
bus_io_read_1(bc, ioh, U24_LMASK),
bus_io_read_1(bc, ioh, U24_SMASK));
bus_space_read_1(iot, ioh, U24_LMASK),
bus_space_read_1(iot, ioh, U24_SMASK));
#endif
bus_io_write_1(bc, ioh, U24_LMASK, 0xd2); /* XXX */
bus_io_write_1(bc, ioh, U24_SMASK, 0x92); /* XXX */
bus_space_write_1(iot, ioh, U24_LMASK, 0xd2); /* XXX */
bus_space_write_1(iot, ioh, U24_SMASK, 0x92); /* XXX */
}

24
sys/dev/ic/aic7xxx.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: aic7xxx.c,v 1.16 1996/10/13 01:37:18 christos Exp $ */
/* $NetBSD: aic7xxx.c,v 1.17 1996/10/21 22:34:04 thorpej Exp $ */
/*
* Generic driver for the aic7xxx based adaptec SCSI controllers
@ -416,10 +416,10 @@ ahc_alloc(unit, iobase, type, flags)
u_long iobase;
#elif defined(__NetBSD__)
void
ahc_construct(ahc, bc, ioh, type, flags)
ahc_construct(ahc, iot, ioh, type, flags)
struct ahc_data *ahc;
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
bus_space_tag_t iot;
bus_space_handle_t ioh;
#endif
ahc_type type;
ahc_flag flags;
@ -453,7 +453,7 @@ ahc_construct(ahc, bc, ioh, type, flags)
#if defined(__FreeBSD__)
ahc->baseport = iobase;
#elif defined(__NetBSD__)
ahc->sc_bc = bc;
ahc->sc_iot = iot;
ahc->sc_ioh = ioh;
#endif
ahc->type = type;
@ -481,10 +481,10 @@ void
ahc_reset(iobase)
u_long iobase;
#elif defined(__NetBSD__)
ahc_reset(devname, bc, ioh)
ahc_reset(devname, iot, ioh)
char *devname;
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
bus_space_tag_t iot;
bus_space_handle_t ioh;
#endif
{
u_char hcntrl;
@ -496,9 +496,9 @@ ahc_reset(devname, bc, ioh)
outb(HCNTRL + iobase, CHIPRST | PAUSE);
#elif defined(__NetBSD__)
hcntrl = (bus_io_read_1(bc, ioh, HCNTRL) & IRQMS) | INTEN;
hcntrl = (bus_space_read_1(iot, ioh, HCNTRL) & IRQMS) | INTEN;
bus_io_write_1(bc, ioh, HCNTRL, CHIPRST | PAUSE);
bus_space_write_1(iot, ioh, HCNTRL, CHIPRST | PAUSE);
#endif
/*
* Ensure that the reset has finished
@ -507,7 +507,7 @@ ahc_reset(devname, bc, ioh)
#if defined(__FreeBSD__)
while (--wait && !(inb(HCNTRL + iobase) & CHIPRSTACK))
#elif defined(__NetBSD__)
while (--wait && !(bus_io_read_1(bc, ioh, HCNTRL) & CHIPRSTACK))
while (--wait && !(bus_space_read_1(iot, ioh, HCNTRL) & CHIPRSTACK))
#endif
DELAY(1000);
if(wait == 0) {
@ -522,7 +522,7 @@ ahc_reset(devname, bc, ioh)
#if defined(__FreeBSD__)
outb(HCNTRL + iobase, hcntrl | PAUSE);
#elif defined(__NetBSD__)
bus_io_write_1(bc, ioh, HCNTRL, hcntrl | PAUSE);
bus_space_write_1(iot, ioh, HCNTRL, hcntrl | PAUSE);
#endif
}

32
sys/dev/ic/aic7xxxvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: aic7xxxvar.h,v 1.9 1996/10/08 03:04:05 gibbs Exp $ */
/* $NetBSD: aic7xxxvar.h,v 1.10 1996/10/21 22:34:09 thorpej Exp $ */
/*
* Interface to the generic driver for the aic7xxx based adaptec
@ -70,15 +70,15 @@
outsl((ahc)->baseport+(port), valp, size)
#elif defined(__NetBSD__)
#define AHC_INB(ahc, port) \
bus_io_read_1((ahc)->sc_bc, (ahc)->sc_ioh, port)
bus_space_read_1((ahc)->sc_iot, (ahc)->sc_ioh, port)
#define AHC_INSB(ahc, port, valp, size) \
bus_io_read_multi_1((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size)
bus_space_read_multi_1((ahc)->sc_iot, (ahc)->sc_ioh, port, valp, size)
#define AHC_OUTB(ahc, port, val) \
bus_io_write_1((ahc)->sc_bc, (ahc)->sc_ioh, port, val)
bus_space_write_1((ahc)->sc_iot, (ahc)->sc_ioh, port, val)
#define AHC_OUTSB(ahc, port, valp, size) \
bus_io_write_multi_1((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size)
bus_space_write_multi_1((ahc)->sc_iot, (ahc)->sc_ioh, port, valp, size)
#define AHC_OUTSL(ahc, port, valp, size) \
bus_io_write_multi_4((ahc)->sc_bc, (ahc)->sc_ioh, port, valp, size)
bus_space_write_multi_4((ahc)->sc_iot, (ahc)->sc_ioh, port, valp, size)
#endif
#define AHC_NSEG 256 /* number of dma segments supported */
@ -211,8 +211,8 @@ struct ahc_data {
#elif defined(__NetBSD__)
struct device sc_dev;
void *sc_ih;
bus_chipset_tag_t sc_bc;
bus_io_handle_t sc_ioh;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
#endif
ahc_type type;
ahc_flag flags;
@ -290,16 +290,18 @@ struct ahc_data *ahc_alloc __P((int unit, u_long io_base, ahc_type type, ahc_fla
#define ahc_name(ahc) (ahc)->sc_dev.dv_xname
void ahc_reset __P((char *devname, bus_chipset_tag_t bc, bus_io_handle_t ioh));
void ahc_construct __P((struct ahc_data *ahc, bus_chipset_tag_t bc, bus_io_handle_t ioh, ahc_type type, ahc_flag flags));
void ahc_reset __P((char *devname, bus_space_tag_t iot,
bus_space_handle_t ioh));
void ahc_construct __P((struct ahc_data *ahc, bus_space_tag_t iot,
bus_space_handle_t ioh, ahc_type type, ahc_flag flags));
#endif
void ahc_free __P((struct ahc_data *));
int ahc_init __P((struct ahc_data *));
int ahc_attach __P((struct ahc_data *));
void ahc_free __P((struct ahc_data *));
int ahc_init __P((struct ahc_data *));
int ahc_attach __P((struct ahc_data *));
#if defined(__FreeBSD__)
void ahc_intr __P((void *arg));
void ahc_intr __P((void *arg));
#elif defined(__NetBSD__)
int ahc_intr __P((void *arg));
int ahc_intr __P((void *arg));
#endif
#endif /* _AIC7XXX_H_ */

135
sys/dev/ic/bha.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: bha.c,v 1.3 1996/10/13 01:37:20 christos Exp $ */
/* $NetBSD: bha.c,v 1.4 1996/10/21 22:34:11 thorpej Exp $ */
#undef BHADIAG
#ifdef DDB
@ -82,8 +82,8 @@
int bha_debug = 0;
#endif /* BHADEBUG */
int bha_cmd __P((bus_chipset_tag_t, bus_io_handle_t, struct bha_softc *, int,
u_char *, int, u_char *));
int bha_cmd __P((bus_space_tag_t, bus_space_handle_t, struct bha_softc *,
int, u_char *, int, u_char *));
integrate void bha_finish_ccbs __P((struct bha_softc *));
integrate void bha_reset_ccb __P((struct bha_softc *, struct bha_ccb *));
void bha_free_ccb __P((struct bha_softc *, struct bha_ccb *));
@ -124,7 +124,7 @@ struct cfdriver bha_cd = {
#define BHA_ABORT_TIMEOUT 2000 /* time to wait for abort (mSec) */
/*
* bha_cmd(bc, ioh, sc, icnt, ibuf, ocnt, obuf)
* bha_cmd(iot, ioh, sc, icnt, ibuf, ocnt, obuf)
*
* Activate Adapter command
* icnt: number of args (outbound bytes including opcode)
@ -138,9 +138,9 @@ struct cfdriver bha_cd = {
* tells it to read in a scsi command.
*/
int
bha_cmd(bc, ioh, sc, icnt, ibuf, ocnt, obuf)
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
bha_cmd(iot, ioh, sc, icnt, ibuf, ocnt, obuf)
bus_space_tag_t iot;
bus_space_handle_t ioh;
struct bha_softc *sc;
int icnt, ocnt;
u_char *ibuf, *obuf;
@ -174,7 +174,7 @@ bha_cmd(bc, ioh, sc, icnt, ibuf, ocnt, obuf)
*/
if (opcode != BHA_MBO_INTR_EN) {
for (i = 20000; i; i--) { /* 1 sec? */
sts = bus_io_read_1(bc, ioh, BHA_STAT_PORT);
sts = bus_space_read_1(iot, ioh, BHA_STAT_PORT);
if (sts & BHA_STAT_IDLE)
break;
delay(50);
@ -190,8 +190,9 @@ bha_cmd(bc, ioh, sc, icnt, ibuf, ocnt, obuf)
* queue feeding to us.
*/
if (ocnt) {
while ((bus_io_read_1(bc, ioh, BHA_STAT_PORT)) & BHA_STAT_DF)
bus_io_read_1(bc, ioh, BHA_DATA_PORT);
while ((bus_space_read_1(iot, ioh, BHA_STAT_PORT)) &
BHA_STAT_DF)
bus_space_read_1(iot, ioh, BHA_DATA_PORT);
}
/*
* Output the command and the number of arguments given
@ -199,18 +200,20 @@ bha_cmd(bc, ioh, sc, icnt, ibuf, ocnt, obuf)
*/
while (icnt--) {
for (i = wait; i; i--) {
sts = bus_io_read_1(bc, ioh, BHA_STAT_PORT);
sts = bus_space_read_1(iot, ioh, BHA_STAT_PORT);
if (!(sts & BHA_STAT_CDF))
break;
delay(50);
}
if (!i) {
if (opcode != BHA_INQUIRE_REVISION)
printf("%s: bha_cmd, cmd/data port full\n", name);
bus_io_write_1(bc, ioh, BHA_CTRL_PORT, BHA_CTRL_SRST);
printf("%s: bha_cmd, cmd/data port full\n",
name);
bus_space_write_1(iot, ioh, BHA_CTRL_PORT,
BHA_CTRL_SRST);
return (1);
}
bus_io_write_1(bc, ioh, BHA_CMD_PORT, *ibuf++);
bus_space_write_1(iot, ioh, BHA_CMD_PORT, *ibuf++);
}
/*
* If we expect input, loop that many times, each time,
@ -218,7 +221,7 @@ bha_cmd(bc, ioh, sc, icnt, ibuf, ocnt, obuf)
*/
while (ocnt--) {
for (i = wait; i; i--) {
sts = bus_io_read_1(bc, ioh, BHA_STAT_PORT);
sts = bus_space_read_1(iot, ioh, BHA_STAT_PORT);
if (sts & BHA_STAT_DF)
break;
delay(50);
@ -227,10 +230,11 @@ bha_cmd(bc, ioh, sc, icnt, ibuf, ocnt, obuf)
if (opcode != BHA_INQUIRE_REVISION)
printf("%s: bha_cmd, cmd/data port empty %d\n",
name, ocnt);
bus_io_write_1(bc, ioh, BHA_CTRL_PORT, BHA_CTRL_SRST);
bus_space_write_1(iot, ioh, BHA_CTRL_PORT,
BHA_CTRL_SRST);
return (1);
}
*obuf++ = bus_io_read_1(bc, ioh, BHA_DATA_PORT);
*obuf++ = bus_space_read_1(iot, ioh, BHA_DATA_PORT);
}
/*
* Wait for the board to report a finished instruction.
@ -239,7 +243,7 @@ bha_cmd(bc, ioh, sc, icnt, ibuf, ocnt, obuf)
*/
if (opcode != BHA_MBO_INTR_EN) {
for (i = 20000; i; i--) { /* 1 sec? */
sts = bus_io_read_1(bc, ioh, BHA_INTR_PORT);
sts = bus_space_read_1(iot, ioh, BHA_INTR_PORT);
/* XXX Need to save this in the interrupt handler? */
if (sts & BHA_INTR_HACC)
break;
@ -251,7 +255,7 @@ bha_cmd(bc, ioh, sc, icnt, ibuf, ocnt, obuf)
return (1);
}
}
bus_io_write_1(bc, ioh, BHA_CTRL_PORT, BHA_CTRL_IRST);
bus_space_write_1(iot, ioh, BHA_CTRL_PORT, BHA_CTRL_IRST);
return (0);
}
@ -379,8 +383,8 @@ bha_intr(arg)
void *arg;
{
struct bha_softc *sc = arg;
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
u_char sts;
#ifdef BHADEBUG
@ -391,10 +395,10 @@ bha_intr(arg)
* First acknowlege the interrupt, Then if it's not telling about
* a completed operation just return.
*/
sts = bus_io_read_1(bc, ioh, BHA_INTR_PORT);
sts = bus_space_read_1(iot, ioh, BHA_INTR_PORT);
if ((sts & BHA_INTR_ANYINTR) == 0)
return (0);
bus_io_write_1(bc, ioh, BHA_CTRL_PORT, BHA_CTRL_IRST);
bus_space_write_1(iot, ioh, BHA_CTRL_PORT, BHA_CTRL_IRST);
#ifdef BHADIAG
/* Make sure we clear CCB_SENDING before finishing a CCB. */
@ -407,7 +411,7 @@ bha_intr(arg)
toggle.cmd.opcode = BHA_MBO_INTR_EN;
toggle.cmd.enable = 0;
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(toggle.cmd), (u_char *)&toggle.cmd,
0, (u_char *)0);
bha_start_ccbs(sc);
@ -592,8 +596,8 @@ void
bha_start_ccbs(sc)
struct bha_softc *sc;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct bha_mbx_out *wmbo; /* Mail Box Out pointer */
struct bha_ccb *ccb;
@ -607,7 +611,7 @@ bha_start_ccbs(sc)
toggle.cmd.opcode = BHA_MBO_INTR_EN;
toggle.cmd.enable = 1;
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(toggle.cmd), (u_char *)&toggle.cmd,
0, (u_char *)0);
break;
@ -627,7 +631,7 @@ bha_start_ccbs(sc)
wmbo->cmd = BHA_MBO_START;
/* Tell the card to poll immediately. */
bus_io_write_1(bc, ioh, BHA_CMD_PORT, BHA_START_SCSI);
bus_space_write_1(iot, ioh, BHA_CMD_PORT, BHA_START_SCSI);
if ((ccb->xs->flags & SCSI_POLL) == 0)
timeout(bha_timeout, ccb, (ccb->timeout * hz) / 1000);
@ -659,13 +663,15 @@ bha_done(sc, ccb)
*/
#ifdef BHADIAG
if (ccb->flags & CCB_SENDING) {
printf("%s: exiting ccb still in transit!\n", sc->sc_dev.dv_xname);
printf("%s: exiting ccb still in transit!\n",
sc->sc_dev.dv_xname);
Debugger();
return;
}
#endif
if ((ccb->flags & CCB_ALLOC) == 0) {
printf("%s: exiting ccb not allocated!\n", sc->sc_dev.dv_xname);
printf("%s: exiting ccb not allocated!\n",
sc->sc_dev.dv_xname);
Debugger();
return;
}
@ -710,9 +716,9 @@ bha_done(sc, ccb)
* Find the board and find it's irq/drq
*/
int
bha_find(bc, ioh, sc)
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
bha_find(iot, ioh, sc)
bus_space_tag_t iot;
bus_space_handle_t ioh;
struct bha_softc *sc;
{
int i;
@ -726,11 +732,12 @@ bha_find(bc, ioh, sc)
* that it's not there.. good for the probe
*/
bus_io_write_1(bc, ioh, BHA_CTRL_PORT, BHA_CTRL_HRST | BHA_CTRL_SRST);
bus_space_write_1(iot, ioh, BHA_CTRL_PORT,
BHA_CTRL_HRST | BHA_CTRL_SRST);
delay(100);
for (i = BHA_RESET_TIMEOUT; i; i--) {
sts = bus_io_read_1(bc, ioh, BHA_STAT_PORT);
sts = bus_space_read_1(iot, ioh, BHA_STAT_PORT);
if (sts == (BHA_STAT_IDLE | BHA_STAT_INIT))
break;
delay(1000);
@ -749,7 +756,7 @@ bha_find(bc, ioh, sc)
delay(1000);
inquire.cmd.opcode = BHA_INQUIRE_EXTENDED;
inquire.cmd.len = sizeof(inquire.reply);
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(inquire.cmd), (u_char *)&inquire.cmd,
sizeof(inquire.reply), (u_char *)&inquire.reply);
switch (inquire.reply.bus_type) {
@ -761,7 +768,8 @@ bha_find(bc, ioh, sc)
/* We don't grok MicroChannel (yet). */
return (0);
default:
printf("bha_find: illegal bus type %c\n", inquire.reply.bus_type);
printf("bha_find: illegal bus type %c\n",
inquire.reply.bus_type);
return (0);
}
@ -771,7 +779,7 @@ bha_find(bc, ioh, sc)
*/
delay(1000);
config.cmd.opcode = BHA_INQUIRE_CONFIG;
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(config.cmd), (u_char *)&config.cmd,
sizeof(config.reply), (u_char *)&config.reply);
switch (config.reply.chan) {
@ -791,7 +799,8 @@ bha_find(bc, ioh, sc)
drq = 7;
break;
default:
printf("bha_find: illegal drq setting %x\n", config.reply.chan);
printf("bha_find: illegal drq setting %x\n",
config.reply.chan);
return (0);
}
@ -815,7 +824,8 @@ bha_find(bc, ioh, sc)
irq = 15;
break;
default:
printf("bha_find: illegal irq setting %x\n", config.reply.intr);
printf("bha_find: illegal irq setting %x\n",
config.reply.intr);
return (0);
}
@ -836,8 +846,8 @@ void
bha_init(sc)
struct bha_softc *sc;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct bha_devices devices;
struct bha_setup setup;
struct bha_mailbox mailbox;
@ -850,21 +860,21 @@ bha_init(sc)
toggle.cmd.opcode = BHA_ROUND_ROBIN;
toggle.cmd.enable = 1;
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(toggle.cmd), (u_char *)&toggle.cmd,
0, (u_char *)0);
}
/* Inquire Installed Devices (to force synchronous negotiation). */
devices.cmd.opcode = BHA_INQUIRE_DEVICES;
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(devices.cmd), (u_char *)&devices.cmd,
sizeof(devices.reply), (u_char *)&devices.reply);
/* Obtain setup information from. */
setup.cmd.opcode = BHA_INQUIRE_SETUP;
setup.cmd.len = sizeof(setup.reply);
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(setup.cmd), (u_char *)&setup.cmd,
sizeof(setup.reply), (u_char *)&setup.reply);
@ -879,14 +889,15 @@ bha_init(sc)
if (sc->sc_firmware[0] >= '3') {
period.cmd.opcode = BHA_INQUIRE_PERIOD;
period.cmd.len = sizeof(period.reply);
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(period.cmd), (u_char *)&period.cmd,
sizeof(period.reply), (u_char *)&period.reply);
}
for (i = 0; i < 8; i++) {
if (!setup.reply.sync[i].valid ||
(!setup.reply.sync[i].offset && !setup.reply.sync[i].period))
(!setup.reply.sync[i].offset &&
!setup.reply.sync[i].period))
continue;
printf("%s targ %d: sync, offset %d, period %dnsec\n",
sc->sc_dev.dv_xname, i,
@ -908,7 +919,7 @@ bha_init(sc)
mailbox.cmd.opcode = BHA_MBX_INIT_EXTENDED;
mailbox.cmd.nmbx = BHA_MBX_SIZE;
ltophys(KVTOPHYS(wmbx), mailbox.cmd.addr);
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(mailbox.cmd), (u_char *)&mailbox.cmd,
0, (u_char *)0);
}
@ -917,8 +928,8 @@ void
bha_inquire_setup_information(sc)
struct bha_softc *sc;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct bha_model model;
struct bha_revision revision;
struct bha_digit digit;
@ -929,21 +940,22 @@ bha_inquire_setup_information(sc)
*/
p = sc->sc_firmware;
revision.cmd.opcode = BHA_INQUIRE_REVISION;
bha_cmd(bc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(revision.cmd), (u_char *)&revision.cmd,
sizeof(revision.reply), (u_char *)&revision.reply);
*p++ = revision.reply.firm_revision;
*p++ = '.';
*p++ = revision.reply.firm_version;
digit.cmd.opcode = BHA_INQUIRE_REVISION_3;
bha_cmd(sc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(digit.cmd), (u_char *)&digit.cmd,
sizeof(digit.reply), (u_char *)&digit.reply);
*p++ = digit.reply.digit;
if (revision.reply.firm_revision >= '3' ||
(revision.reply.firm_revision == '3' && revision.reply.firm_version >= '3')) {
(revision.reply.firm_revision == '3' &&
revision.reply.firm_version >= '3')) {
digit.cmd.opcode = BHA_INQUIRE_REVISION_4;
bha_cmd(sc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(digit.cmd), (u_char *)&digit.cmd,
sizeof(digit.reply), (u_char *)&digit.reply);
*p++ = digit.reply.digit;
@ -959,7 +971,7 @@ bha_inquire_setup_information(sc)
p = sc->sc_model;
model.cmd.opcode = BHA_INQUIRE_MODEL;
model.cmd.len = sizeof(model.reply);
bha_cmd(sc, ioh, sc,
bha_cmd(iot, ioh, sc,
sizeof(model.cmd), (u_char *)&model.cmd,
sizeof(model.reply), (u_char *)&model.reply);
*p++ = model.reply.id[0];
@ -1076,7 +1088,8 @@ bha_scsi_cmd(xs)
/* put in the base address */
ltophys(thisphys, sg->seg_addr);
SC_DEBUGN(sc_link, SDEV_DB4, ("0x%x", thisphys));
SC_DEBUGN(sc_link, SDEV_DB4,
("0x%x", thisphys));
/* do it at least once */
nextphys = thisphys;
@ -1087,7 +1100,8 @@ bha_scsi_cmd(xs)
* length
*/
/* how far to the end of the page */
nextphys = (thisphys & ~PGOFSET) + NBPG;
nextphys =
(thisphys & ~PGOFSET) + NBPG;
bytes_this_page = nextphys - thisphys;
/**** or the data ****/
bytes_this_page = min(bytes_this_page,
@ -1174,8 +1188,8 @@ bha_poll(sc, xs, count)
struct scsi_xfer *xs;
int count;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
/* timeouts are in msec, so we loop in 1000 usec cycles */
while (count) {
@ -1183,7 +1197,8 @@ bha_poll(sc, xs, count)
* If we had interrupts enabled, would we
* have got an interrupt?
*/
if (bus_io_read_1(bc, ioh, BHA_INTR_PORT) & BHA_INTR_ANYINTR)
if (bus_space_read_1(iot, ioh, BHA_INTR_PORT) &
BHA_INTR_ANYINTR)
bha_intr(sc);
if (xs->flags & ITSDONE)
return (0);

9
sys/dev/ic/bhavar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: bhavar.h,v 1.2 1996/09/01 00:54:38 mycroft Exp $ */
/* $NetBSD: bhavar.h,v 1.3 1996/10/21 22:34:13 thorpej Exp $ */
/*
* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
@ -56,9 +56,9 @@ struct bha_mbx {
struct bha_softc {
struct device sc_dev;
bus_chipset_tag_t sc_bc;
bus_space_tag_t sc_iot;
bus_io_handle_t sc_ioh;
bus_space_handle_t sc_ioh;
int sc_irq, sc_drq;
void *sc_ih;
@ -74,6 +74,7 @@ struct bha_softc {
struct scsi_link sc_link; /* prototype for devs */
};
int bha_find __P((bus_chipset_tag_t, bus_io_handle_t, struct bha_softc *));
int bha_find __P((bus_space_tag_t, bus_space_handle_t,
struct bha_softc *));
void bha_attach __P((struct bha_softc *));
int bha_intr __P((void *));

28
sys/dev/ic/cy.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cy.c,v 1.4 1996/10/13 01:37:21 christos Exp $ */
/* $NetBSD: cy.c,v 1.5 1996/10/21 22:34:15 thorpej Exp $ */
/*
* cy.c
@ -17,9 +17,6 @@
* Lots of debug output can be enabled by defining CY_DEBUG
* Some debugging counters (number of receive/transmit interrupts etc.)
* can be enabled by defining CY_DEBUG1
*
* This version uses the bus_mem/io_??() stuff
*
*/
#include <sys/types.h>
@ -36,6 +33,7 @@
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/systm.h>
#include <machine/bus.h>
#include <dev/ic/cd1400reg.h>
@ -74,14 +72,14 @@ cy_find(sc)
{
int cy_chip, chip;
u_char firmware_ver;
bus_chipset_tag_t bc = sc->sc_bc;
bus_mem_handle_t memh = sc->sc_memh;
bus_space_tag_t tag = sc->sc_memt;
bus_space_handle_t bsh = sc->sc_bsh;
int bustype = sc->sc_bustype;
/* Cyclom card hardware reset */
bus_mem_write_1(bc, memh, CY16_RESET << bustype, 0);
bus_space_write_1(tag, bsh, CY16_RESET << bustype, 0);
DELAY(500); /* wait for reset to complete */
bus_mem_write_1(bc, memh, CY_CLEAR_INTR << bustype, 0);
bus_space_write_1(tag, bsh, CY_CLEAR_INTR << bustype, 0);
#ifdef CY_DEBUG
printf("cy: card reset done\n");
@ -106,7 +104,7 @@ cy_find(sc)
/* wait until the chip is ready for command */
DELAY(1000);
if (bus_mem_read_1(bc, memh, chip +
if (bus_space_read_1(tag, bsh, chip +
((CD1400_CCR << 1) << bustype)) != 0) {
#ifdef CY_DEBUG
printf("not ready for command\n");
@ -114,7 +112,7 @@ cy_find(sc)
break;
}
/* clear the firmware version reg. */
bus_mem_write_1(bc, memh, chip +
bus_space_write_1(tag, bsh, chip +
((CD1400_GFRCR << 1) << bustype), 0);
/*
@ -124,19 +122,19 @@ cy_find(sc)
* cleared chip 0 GFRCR. In that case we have a 16 port card.
*/
if (cy_chip == 4 &&
bus_mem_read_1(bc, memh, chip +
bus_space_read_1(tag, bsh, chip +
((CD1400_GFRCR << 1) << bustype)) == 0)
break;
/* reset the chip */
bus_mem_write_1(bc, memh, chip +
bus_space_write_1(tag, bsh, chip +
((CD1400_CCR << 1) << bustype),
CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET);
/* wait for the chip to initialize itself */
for (i = 0; i < 200; i++) {
DELAY(50);
firmware_ver = bus_mem_read_1(bc, memh, chip +
firmware_ver = bus_space_read_1(tag, bsh, chip +
((CD1400_GFRCR << 1) << bustype));
if ((firmware_ver & 0xf0) == 0x40) /* found a CD1400 */
break;
@ -214,7 +212,7 @@ cy_attach(parent, self, aux)
printf(" (%d ports)\n", port);
/* ensure an edge for the next interrupt */
bus_mem_write_1(sc->sc_bc, sc->sc_memh,
bus_space_write_1(sc->sc_memt, sc->sc_bsh,
CY_CLEAR_INTR << sc->sc_bustype, 0);
}
@ -1314,7 +1312,7 @@ cy_intr(arg)
} /* for(...all CD1400s on a card) */
/* ensure an edge for next interrupt */
bus_mem_write_1(sc->sc_bc, sc->sc_memh,
bus_space_write_1(sc->sc_memt, sc->sc_bsh,
CY_CLEAR_INTR << sc->sc_bustype, 0);
return int_serviced;
}

15
sys/dev/ic/cyvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cyvar.h,v 1.1 1996/09/24 18:02:36 christos Exp $ */
/* $NetBSD: cyvar.h,v 1.2 1996/10/21 22:34:19 thorpej Exp $ */
/*
* cy_var.h
@ -40,12 +40,12 @@
/*
* read/write cd1400 registers (when sc_softc-structure is available)
*/
#define cd_read_reg(sc,chip,reg) bus_mem_read_1(sc->sc_bc, \
sc->sc_memh, sc->sc_cd1400_offs[chip] + \
#define cd_read_reg(sc,chip,reg) bus_space_read_1(sc->sc_memt, \
sc->sc_bsh, sc->sc_cd1400_offs[chip] + \
(((reg << 1)) << sc->sc_bustype))
#define cd_write_reg(sc,chip,reg,val) bus_mem_write_1(sc->sc_bc, \
sc->sc_memh, sc->sc_cd1400_offs[chip] + \
#define cd_write_reg(sc,chip,reg,val) bus_space_write_1(sc->sc_memt, \
sc->sc_bsh, sc->sc_cd1400_offs[chip] + \
(((reg << 1))<< sc->sc_bustype), (val))
/*
@ -87,8 +87,9 @@ struct cy_port {
struct cy_softc {
struct device sc_dev;
void *sc_ih;
bus_chipset_tag_t sc_bc;
bus_mem_handle_t sc_memh;
bus_space_tag_t sc_memt;
bus_space_tag_t sc_iot; /* only used by PCI card */
bus_space_handle_t sc_bsh;
int sc_bustype;
int sc_nchips; /* Number of cd1400's on this card */
int sc_cd1400_offs[CY_MAX_CD1400s];

193
sys/dev/ic/elink3.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: elink3.c,v 1.10 1996/10/13 01:37:22 christos Exp $ */
/* $NetBSD: elink3.c,v 1.11 1996/10/21 22:34:21 thorpej Exp $ */
/*
* Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
@ -103,8 +103,8 @@ epconfig(sc, conn)
u_int16_t conn;
{
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
u_int16_t i;
sc->ep_connectors = 0;
@ -135,10 +135,11 @@ epconfig(sc, conn)
u_int16_t x;
if (epbusyeeprom(sc))
return;
bus_io_write_2(bc, ioh, EP_W0_EEPROM_COMMAND, READ_EEPROM | i);
bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND,
READ_EEPROM | i);
if (epbusyeeprom(sc))
return;
x = bus_io_read_2(bc, ioh, EP_W0_EEPROM_DATA);
x = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA);
sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8;
sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x;
}
@ -173,48 +174,48 @@ epinit(sc)
register struct ep_softc *sc;
{
register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int i;
while (bus_io_read_2(bc, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
;
if (sc->bustype != EP_BUS_PCI) {
GO_WINDOW(0);
bus_io_write_2(bc, ioh, EP_W0_CONFIG_CTRL, 0);
bus_io_write_2(bc, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0);
bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
}
if (sc->bustype == EP_BUS_PCMCIA) {
#ifdef EP_COAX_DEFAULT
bus_io_write_2(bc, ioh, EP_W0_ADDRESS_CFG,3<<14);
bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG,3<<14);
#else
bus_io_write_2(bc, ioh, EP_W0_ADDRESS_CFG,0<<14);
bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG,0<<14);
#endif
bus_io_write_2(bc, ioh, EP_W0_RESOURCE_CFG, 0x3f00);
bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00);
}
GO_WINDOW(2);
for (i = 0; i < 6; i++) /* Reload the ether_addr. */
bus_io_write_1(bc, ioh, EP_W2_ADDR_0 + i,
bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i,
sc->sc_arpcom.ac_enaddr[i]);
if (sc->bustype == EP_BUS_PCI || sc->bustype == EP_BUS_EISA)
/* Reset the station-address receive filter */
for (i = 0; i < 6; i++)
bus_io_write_1(bc, ioh,EP_W2_RECVMASK_0 + i, 0);
bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0);
bus_io_write_2(bc, ioh, EP_COMMAND, RX_RESET);
bus_io_write_2(bc, ioh, EP_COMMAND, TX_RESET);
bus_space_write_2(iot, ioh, EP_COMMAND, RX_RESET);
bus_space_write_2(iot, ioh, EP_COMMAND, TX_RESET);
GO_WINDOW(1); /* Window 1 is operating window */
for (i = 0; i < 31; i++)
bus_io_read_1(bc, ioh, EP_W1_TX_STATUS);
bus_space_read_1(iot, ioh, EP_W1_TX_STATUS);
bus_io_write_2(bc, ioh, EP_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE |
bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE |
S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
bus_io_write_2(bc, ioh, EP_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |
bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |
S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL);
/*
@ -223,13 +224,13 @@ epinit(sc)
* already be queued. However, a single stray interrupt is
* unimportant.
*/
bus_io_write_2(bc, ioh, EP_COMMAND, ACK_INTR | 0xff);
bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff);
epsetfilter(sc);
epsetlink(sc);
bus_io_write_2(bc, ioh, EP_COMMAND, RX_ENABLE);
bus_io_write_2(bc, ioh, EP_COMMAND, TX_ENABLE);
bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE);
bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE);
epmbuffill(sc);
@ -248,7 +249,7 @@ epsetfilter(sc)
register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
GO_WINDOW(1); /* Window 1 is operating window */
bus_io_write_2(sc->sc_bc, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER |
bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER |
FIL_INDIVIDUAL | FIL_BRDCST |
((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) |
((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 ));
@ -259,8 +260,8 @@ epsetlink(sc)
register struct ep_softc *sc;
{
register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
/*
* you can `ifconfig (link0|-link0) ep0' to get the following
@ -271,27 +272,27 @@ epsetlink(sc)
* set too, then you get the UTP port.
*/
GO_WINDOW(4);
bus_io_write_2(bc, ioh, EP_W4_MEDIA_TYPE, DISABLE_UTP);
bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, DISABLE_UTP);
if (!(ifp->if_flags & IFF_LINK0) && (sc->ep_connectors & BNC)) {
if (sc->bustype == EP_BUS_PCMCIA) {
GO_WINDOW(0);
bus_io_write_2(bc, ioh, EP_W0_ADDRESS_CFG,3<<14);
bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG,3<<14);
GO_WINDOW(1);
}
bus_io_write_2(bc, ioh, EP_COMMAND, START_TRANSCEIVER);
bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER);
delay(1000);
}
if (ifp->if_flags & IFF_LINK0) {
bus_io_write_2(bc, ioh, EP_COMMAND, STOP_TRANSCEIVER);
bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER);
delay(1000);
if ((ifp->if_flags & IFF_LINK1) && (sc->ep_connectors & UTP)) {
if (sc->bustype == EP_BUS_PCMCIA) {
GO_WINDOW(0);
bus_io_write_2(bc, ioh,
bus_space_write_2(iot, ioh,
EP_W0_ADDRESS_CFG,0<<14);
GO_WINDOW(4);
}
bus_io_write_2(bc, ioh, EP_W4_MEDIA_TYPE, ENABLE_UTP);
bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, ENABLE_UTP);
}
}
GO_WINDOW(1);
@ -306,8 +307,8 @@ epstart(ifp)
struct ifnet *ifp;
{
register struct ep_softc *sc = ifp->if_softc;
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct mbuf *m, *m0;
int sh, len, pad;
@ -341,14 +342,14 @@ startagain:
goto readcheck;
}
if (bus_io_read_2(bc, ioh, EP_W1_FREE_TX) < len + pad + 4) {
bus_io_write_2(bc, ioh, EP_COMMAND,
if (bus_space_read_2(iot, ioh, EP_W1_FREE_TX) < len + pad + 4) {
bus_space_write_2(iot, ioh, EP_COMMAND,
SET_TX_AVAIL_THRESH | (len + pad + 4));
/* not enough room in FIFO */
ifp->if_flags |= IFF_OACTIVE;
return;
} else {
bus_io_write_2(bc, ioh, EP_COMMAND,
bus_space_write_2(iot, ioh, EP_COMMAND,
SET_TX_AVAIL_THRESH | 2044);
}
@ -356,7 +357,7 @@ startagain:
if (m0 == 0) /* not really needed */
return;
bus_io_write_2(bc, ioh, EP_COMMAND, SET_TX_START_THRESH |
bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH |
(len / 4 + sc->tx_start_thresh));
#if NBPFILTER > 0
@ -370,17 +371,17 @@ startagain:
*/
sh = splhigh();
bus_io_write_2(bc, ioh, EP_W1_TX_PIO_WR_1, len);
bus_io_write_2(bc, ioh, EP_W1_TX_PIO_WR_1,
bus_space_write_2(iot, ioh, EP_W1_TX_PIO_WR_1, len);
bus_space_write_2(iot, ioh, EP_W1_TX_PIO_WR_1,
0xffff); /* Second dword meaningless */
if (EP_IS_BUS_32(sc->bustype)) {
for (m = m0; m; ) {
if (m->m_len > 3)
bus_io_write_multi_4(bc, ioh,
bus_space_write_multi_4(iot, ioh,
EP_W1_TX_PIO_WR_1, mtod(m, u_int32_t *),
m->m_len / 4);
if (m->m_len & 3)
bus_io_write_multi_1(bc, ioh,
bus_space_write_multi_1(iot, ioh,
EP_W1_TX_PIO_WR_1,
mtod(m, u_int8_t *) + (m->m_len & ~3),
m->m_len & 3);
@ -390,27 +391,27 @@ startagain:
} else {
for (m = m0; m; ) {
if (m->m_len > 1)
bus_io_write_multi_2(bc, ioh,
bus_space_write_multi_2(iot, ioh,
EP_W1_TX_PIO_WR_1, mtod(m, u_int16_t *),
m->m_len / 2);
if (m->m_len & 1)
bus_io_write_1(bc, ioh, EP_W1_TX_PIO_WR_1,
bus_space_write_1(iot, ioh, EP_W1_TX_PIO_WR_1,
*(mtod(m, u_int8_t *) + m->m_len - 1));
MFREE(m, m0);
m = m0;
}
}
while (pad--)
bus_io_write_1(bc, ioh, EP_W1_TX_PIO_WR_1, 0);
bus_space_write_1(iot, ioh, EP_W1_TX_PIO_WR_1, 0);
splx(sh);
++ifp->if_opackets;
readcheck:
if ((bus_io_read_2(bc, ioh, EP_W1_RX_STATUS) & ERR_INCOMPLETE) == 0) {
if ((bus_space_read_2(iot, ioh, EP_W1_RX_STATUS) & ERR_INCOMPLETE) == 0) {
/* We received a complete packet. */
u_int16_t status = bus_io_read_2(bc, ioh, EP_STATUS);
u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS);
if ((status & S_INTR_LATCH) == 0) {
/*
@ -449,15 +450,15 @@ static int
epstatus(sc)
register struct ep_softc *sc;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
u_int16_t fifost;
/*
* Check the FIFO status and act accordingly
*/
GO_WINDOW(4);
fifost = bus_io_read_2(bc, ioh, EP_W4_FIFO_DIAG);
fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG);
GO_WINDOW(1);
if (fifost & FIFOS_RX_UNDERRUN) {
@ -494,16 +495,16 @@ static void
eptxstat(sc)
register struct ep_softc *sc;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int i;
/*
* We need to read+write TX_STATUS until we get a 0 status
* in order to turn off the interrupt flag.
*/
while ((i = bus_io_read_1(bc, ioh, EP_W1_TX_STATUS)) & TXS_COMPLETE) {
bus_io_write_1(bc, ioh, EP_W1_TX_STATUS, 0x0);
while ((i = bus_space_read_1(iot, ioh, EP_W1_TX_STATUS)) & TXS_COMPLETE) {
bus_space_write_1(iot, ioh, EP_W1_TX_STATUS, 0x0);
if (i & TXS_JABBER) {
++sc->sc_arpcom.ac_if.if_oerrors;
@ -524,7 +525,7 @@ eptxstat(sc)
epreset(sc);
} else if (i & TXS_MAX_COLLISION) {
++sc->sc_arpcom.ac_if.if_collisions;
bus_io_write_2(bc, ioh, EP_COMMAND, TX_ENABLE);
bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE);
sc->sc_arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
} else
sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127;
@ -536,16 +537,16 @@ epintr(arg)
void *arg;
{
register struct ep_softc *sc = arg;
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
u_int16_t status;
int ret = 0;
for (;;) {
bus_io_write_2(bc, ioh, EP_COMMAND, C_INTR_LATCH);
bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH);
status = bus_io_read_2(bc, ioh, EP_STATUS);
status = bus_space_read_2(iot, ioh, EP_STATUS);
if ((status & (S_TX_COMPLETE | S_TX_AVAIL |
S_RX_COMPLETE | S_CARD_FAILURE)) == 0)
@ -559,7 +560,7 @@ epintr(arg)
* Due to the i386 interrupt queueing, we may get spurious
* interrupts occasionally.
*/
bus_io_write_2(bc, ioh, EP_COMMAND, ACK_INTR | status);
bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status);
if (status & S_RX_COMPLETE)
epread(sc);
@ -587,14 +588,14 @@ void
epread(sc)
register struct ep_softc *sc;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct mbuf *m;
struct ether_header *eh;
int len;
len = bus_io_read_2(bc, ioh, EP_W1_RX_STATUS);
len = bus_space_read_2(iot, ioh, EP_W1_RX_STATUS);
again:
if (ifp->if_flags & IFF_DEBUG) {
@ -686,7 +687,7 @@ again:
* I'll modify epread() so that it can handle RX_EARLY interrupts.
*/
if (epstatus(sc)) {
len = bus_io_read_2(bc, ioh, EP_W1_RX_STATUS);
len = bus_space_read_2(iot, ioh, EP_W1_RX_STATUS);
/* Check if we are stuck and reset [see XXX comment] */
if (len & ERR_INCOMPLETE) {
if (ifp->if_flags & IFF_DEBUG)
@ -701,8 +702,8 @@ again:
return;
abort:
bus_io_write_2(bc, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
while (bus_io_read_2(bc, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
;
}
@ -711,8 +712,8 @@ epget(sc, totlen)
struct ep_softc *sc;
int totlen;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct mbuf *top, **mp, *m;
int len;
@ -771,22 +772,22 @@ epget(sc, totlen)
if (EP_IS_BUS_32(sc->bustype)) {
if (len > 3) {
len &= ~3;
bus_io_read_multi_4(bc, ioh,
bus_space_read_multi_4(iot, ioh,
EP_W1_RX_PIO_RD_1, mtod(m, u_int32_t *),
len / 4);
} else
bus_io_read_multi_1(bc, ioh,
bus_space_read_multi_1(iot, ioh,
EP_W1_RX_PIO_RD_1, mtod(m, u_int8_t *),
len);
} else {
if (len > 1) {
len &= ~1;
bus_io_read_multi_2(bc, ioh,
bus_space_read_multi_2(iot, ioh,
EP_W1_RX_PIO_RD_1, mtod(m, u_int16_t *),
len / 2);
} else
*(mtod(m, u_int8_t *)) =
bus_io_read_1(bc, ioh, EP_W1_RX_PIO_RD_1);
bus_space_read_1(iot, ioh, EP_W1_RX_PIO_RD_1);
}
m->m_len = len;
totlen -= len;
@ -794,8 +795,8 @@ epget(sc, totlen)
mp = &m->m_next;
}
bus_io_write_2(bc, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
while (bus_io_read_2(bc, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
;
splx(sh);
@ -931,21 +932,21 @@ void
epstop(sc)
register struct ep_softc *sc;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
bus_io_write_2(bc, ioh, EP_COMMAND, RX_DISABLE);
bus_io_write_2(bc, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
while (bus_io_read_2(bc, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE);
bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK);
while (bus_space_read_2(iot, ioh, EP_STATUS) & S_COMMAND_IN_PROGRESS)
;
bus_io_write_2(bc, ioh, EP_COMMAND, TX_DISABLE);
bus_io_write_2(bc, ioh, EP_COMMAND, STOP_TRANSCEIVER);
bus_io_write_2(bc, ioh, EP_COMMAND, RX_RESET);
bus_io_write_2(bc, ioh, EP_COMMAND, TX_RESET);
bus_io_write_2(bc, ioh, EP_COMMAND, C_INTR_LATCH);
bus_io_write_2(bc, ioh, EP_COMMAND, SET_RD_0_MASK);
bus_io_write_2(bc, ioh, EP_COMMAND, SET_INTR_MASK);
bus_io_write_2(bc, ioh, EP_COMMAND, SET_RX_FILTER);
bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE);
bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER);
bus_space_write_2(iot, ioh, EP_COMMAND, RX_RESET);
bus_space_write_2(iot, ioh, EP_COMMAND, TX_RESET);
bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH);
bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK);
bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK);
bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER);
epmbufempty(sc);
}
@ -961,24 +962,24 @@ epstop(sc)
* each card compares the data on the bus; if there is a difference
* then that card goes into ID_WAIT state again). In the meantime;
* one bit of data is returned in the AX register which is conveniently
* returned to us by bus_io_read_1(). Hence; we read 16 times getting one
* returned to us by bus_space_read_1(). Hence; we read 16 times getting one
* bit of data with each read.
*
* NOTE: the caller must provide an i/o handle for ELINK_ID_PORT!
*/
u_int16_t
epreadeeprom(bc, ioh, offset)
bus_chipset_tag_t bc;
bus_io_handle_t ioh;
epreadeeprom(iot, ioh, offset)
bus_space_tag_t iot;
bus_space_handle_t ioh;
int offset;
{
u_int16_t data = 0;
int i;
bus_io_write_1(bc, ioh, 0, 0x80 + offset);
bus_space_write_1(iot, ioh, 0, 0x80 + offset);
delay(1000);
for (i = 0; i < 16; i++)
data = (data << 1) | (bus_io_read_2(bc, ioh, 0) & 1);
data = (data << 1) | (bus_space_read_2(iot, ioh, 0) & 1);
return (data);
}
@ -986,8 +987,8 @@ static int
epbusyeeprom(sc)
struct ep_softc *sc;
{
bus_chipset_tag_t bc = sc->sc_bc;
bus_io_handle_t ioh = sc->sc_ioh;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
int i = 100, j;
if (sc->bustype == EP_BUS_PCMCIA) {
@ -996,7 +997,7 @@ epbusyeeprom(sc)
}
while (i--) {
j = bus_io_read_2(bc, ioh, EP_W0_EEPROM_COMMAND);
j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND);
if (j & EEPROM_BUSY)
delay(100);
else

4
sys/dev/ic/elink3reg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: elink3reg.h,v 1.4 1996/09/29 11:19:43 christos Exp $ */
/* $NetBSD: elink3reg.h,v 1.5 1996/10/21 22:34:23 thorpej Exp $ */
/*
* Copyright (c) 1995 Herb Peyerl <hpeyerl@beer.org>
@ -331,7 +331,7 @@
#define ENABLE_DRQ_IRQ 0x0001
#define MFG_ID 0x506d /* `TCM' */
#define PROD_ID 0x5090
#define GO_WINDOW(x) bus_io_write_2(sc->sc_bc, \
#define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \
sc->sc_ioh, EP_COMMAND, WINDOW_SELECT|x)
#define AUI 0x1
#define BNC 0x2

8
sys/dev/ic/elink3var.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: elink3var.h,v 1.5 1996/05/14 22:22:06 thorpej Exp $ */
/* $NetBSD: elink3var.h,v 1.6 1996/10/21 22:34:25 thorpej Exp $ */
/*
* Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
@ -38,8 +38,8 @@ struct ep_softc {
void *sc_ih;
struct arpcom sc_arpcom; /* Ethernet common part */
bus_chipset_tag_t sc_bc; /* bus cookie */
bus_io_handle_t sc_ioh; /* bus i/o handle */
bus_space_tag_t sc_iot; /* bus cookie */
bus_space_handle_t sc_ioh; /* bus i/o handle */
char ep_connectors; /* Connectors on this card. */
#define MAX_MBS 8 /* # of mbufs we keep around */
struct mbuf *mb[MAX_MBS]; /* spare mbuf storage. */
@ -57,7 +57,7 @@ struct ep_softc {
#define EP_IS_BUS_32(a) ((a) & 0x2)
};
u_int16_t epreadeeprom __P((bus_chipset_tag_t, bus_io_handle_t, int));
u_int16_t epreadeeprom __P((bus_space_tag_t, bus_space_handle_t, int));
void epconfig __P((struct ep_softc *, u_int16_t));
int epintr __P((void *));
void epstop __P((struct ep_softc *));

16
sys/dev/ic/midway.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: midway.c,v 1.17 1996/10/13 01:37:24 christos Exp $ */
/* $NetBSD: midway.c,v 1.18 1996/10/21 22:34:27 thorpej Exp $ */
/* (sync'd to midway.c 1.62) */
/*
@ -123,7 +123,7 @@
#if defined(__alpha__)
/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
#undef vtophys
#define vtophys(va) __alpha_bus_XXX_dmamap(sc->en_bc, (void *)(va))
#define vtophys(va) __alpha_bus_XXX_dmamap(sc->en_memt, (void *)(va))
#endif
#elif defined(__FreeBSD__)
#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */
@ -241,7 +241,7 @@ u_int32_t r;
printf("en_read out of range, r=0x%x\n", r);
panic("en_read");
}
return(bus_mem_read_4(sc->en_bc, sc->en_base, r));
return(bus_space_read_4(sc->en_memt, sc->en_base, r));
}
#define EN_READ(SC,R) ntohl(en_read(SC,R))
#define EN_READDAT(SC,R) en_read(SC,R)
@ -256,20 +256,20 @@ u_int32_t r, v;
printf("en_write out of range, r=0x%x\n", r);
panic("en_write");
}
bus_mem_write_4(sc->en_bc, sc->en_base, r, v);
bus_space_write_4(sc->en_memt, sc->en_base, r, v);
}
#define EN_WRITE(SC,R,V) en_write(SC,R, htonl(V))
#define EN_WRITEDAT(SC,R,V) en_write(SC,R,V)
#else /* EN_DEBUG_RANGE */
#define EN_READ(SC,R) ntohl(bus_mem_read_4((SC)->en_bc, (SC)->en_base, (R)))
#define EN_READ(SC,R) ntohl(bus_space_read_4((SC)->en_memt, (SC)->en_base, (R)))
#define EN_WRITE(SC,R,V) \
bus_mem_write_4((SC)->en_bc, (SC)->en_base, (R), htonl((V)))
bus_space_write_4((SC)->en_memt, (SC)->en_base, (R), htonl((V)))
#define EN_READDAT(SC,R) bus_mem_read_4((SC)->en_bc, (SC)->en_base, (R))
#define EN_READDAT(SC,R) bus_space_read_4((SC)->en_memt, (SC)->en_base, (R))
#define EN_WRITEDAT(SC,R,V) \
bus_mem_write_4((SC)->en_bc, (SC)->en_base, (R), (V))
bus_space_write_4((SC)->en_memt, (SC)->en_base, (R), (V))
#define EN_WRAPADD(START,STOP,CUR,VAL) { \
(CUR) = (CUR) + (VAL); \

23
sys/dev/ic/midwayreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: midwayreg.h,v 1.4 1996/07/16 22:11:05 chuck Exp $ */
/* $NetBSD: midwayreg.h,v 1.5 1996/10/21 22:34:30 thorpej Exp $ */
/*
* m i d w a y r e g . h
@ -10,14 +10,15 @@
#if defined(sparc) || defined(__FreeBSD__)
/* XXX: gross. netbsd/sparc doesn't have machine/bus.h yet. */
typedef void * bus_chipset_tag_t;
typedef void * bus_space_tag_t;
typedef u_int32_t pci_chipset_tag_t;
typedef caddr_t bus_mem_handle_t;
typedef u_int32_t bus_mem_size_t;
typedef caddr_t bus_mem_addr_t;
typedef caddr_t bus_space_handle_t;
typedef u_int32_t bus_size_t;
typedef caddr_t bus_addr_t;
#define bus_mem_read_4(t, h, o) ((void) t, (*(volatile u_int32_t *)((h) + (o))))
#define bus_mem_write_4(t, h, o, v) \
#define bus_space_read_4(t, h, o) ((void) t, \
(*(volatile u_int32_t *)((h) + (o))))
#define bus_space_write_4(t, h, o, v) \
((void) t, ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))))
#if defined(sparc)
@ -38,12 +39,12 @@ typedef caddr_t bus_mem_addr_t;
* card data structures, top down
*
* in order to have a portable driver, the netbsd guys will not let us
* use structs. we have a bus_mem_handle_t which is the en_base address.
* use structs. we have a bus_space_handle_t which is the en_base address.
* everything else is an offset from that base. all card data must be
* accessed with bus_mem_read_4()/bus_mem_write_4():
* accessed with bus_space_read_4()/bus_space_write_4():
*
* rv = bus_mem_read_4(sc->en_bc, sc->en_base, BYTE_OFFSET);
* bus_mem_write_4(sc->en_bc, sc->en_base, BYTE_OFFSET, VALUE);
* rv = bus_space_read_4(sc->en_memt, sc->en_base, BYTE_OFFSET);
* bus_space_write_4(sc->en_memt, sc->en_base, BYTE_OFFSET, VALUE);
*
* en_card: the whole card (prom + phy + midway + obmem)
* obmem contains: vci tab + dma queues (rx & tx) + service list + bufs

8
sys/dev/ic/midwayvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: midwayvar.h,v 1.7 1996/07/16 22:11:11 chuck Exp $ */
/* $NetBSD: midwayvar.h,v 1.8 1996/10/21 22:34:33 thorpej Exp $ */
/*
*
@ -101,9 +101,9 @@ struct en_softc {
struct ifnet enif; /* network ifnet handle */
/* bus glue */
bus_chipset_tag_t en_bc; /* for EN_READ/EN_WRITE */
bus_mem_handle_t en_base; /* base of en card */
bus_mem_size_t en_obmemsz; /* size of en card (bytes) */
bus_space_tag_t en_memt; /* for EN_READ/EN_WRITE */
bus_space_handle_t en_base; /* base of en card */
bus_size_t en_obmemsz; /* size of en card (bytes) */
/* serv list */
u_int32_t hwslistp; /* hw pointer to service list (byte offset) */

34
sys/dev/ic/pdqvar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pdqvar.h,v 1.8 1996/07/10 18:55:05 cgd Exp $ */
/* $NetBSD: pdqvar.h,v 1.9 1996/10/21 22:34:36 thorpej Exp $ */
/*-
* Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
@ -130,21 +130,17 @@ typedef pdq_bus_memaddr_t pdq_bus_memoffset_t;
#define PDQ_OS_PTR_FMT "%p"
typedef void ifnet_ret_t;
typedef u_long ioctl_cmd_t;
typedef bus_chipset_tag_t pdq_bus_t;
typedef bus_io_handle_t pdq_bus_ioport_t;
#if defined(PDQ_IOMAPPED)
typedef bus_io_handle_t pdq_bus_memaddr_t;
#else
typedef bus_mem_handle_t pdq_bus_memaddr_t;
#endif
typedef bus_space_tag_t pdq_bus_t;
typedef bus_space_handle_t pdq_bus_ioport_t;
typedef bus_space_handle_t pdq_bus_memaddr_t;
typedef pdq_uint32_t pdq_bus_memoffset_t;
#define PDQ_OS_IOMEM
#define PDQ_OS_IORD_32(t, base, offset) bus_io_read_4 (t, base, offset)
#define PDQ_OS_IOWR_32(t, base, offset, data) bus_io_write_4 (t, base, offset, data)
#define PDQ_OS_IORD_8(t, base, offset) bus_io_read_1 (t, base, offset)
#define PDQ_OS_IOWR_8(t, base, offset, data) bus_io_write_1 (t, base, offset, data)
#define PDQ_OS_MEMRD_32(t, base, offset) bus_mem_read_4(t, base, offset)
#define PDQ_OS_MEMWR_32(t, base, offset, data) bus_mem_write_4(t, base, offset, data)
#define PDQ_OS_IORD_32(t, base, offset) bus_space_read_4 (t, base, offset)
#define PDQ_OS_IOWR_32(t, base, offset, data) bus_space_write_4 (t, base, offset, data)
#define PDQ_OS_IORD_8(t, base, offset) bus_space_read_1 (t, base, offset)
#define PDQ_OS_IOWR_8(t, base, offset, data) bus_space_write_1 (t, base, offset, data)
#define PDQ_OS_MEMRD_32(t, base, offset) bus_space_read_4(t, base, offset)
#define PDQ_OS_MEMWR_32(t, base, offset, data) bus_space_write_4(t, base, offset, data)
#define PDQ_CSR_OFFSET(base, offset) (0 + (offset)*sizeof(pdq_uint32_t))
#if defined(PDQ_IOMAPPED)
@ -198,21 +194,27 @@ typedef struct {
struct device sc_dev; /* base device */
void *sc_ih; /* interrupt vectoring */
void *sc_ats; /* shutdown hook */
bus_space_tag_t sc_csrtag; /* space tag for CSRs */
bus_space_handle_t sc_csrhandle; /* space handle for CSRs */
#define sc_bc sc_csrtag
#define sc_membase sc_csrhandle
bus_space_tag_t sc_iotag; /* i/o space tag */
bus_space_handle_t sc_iobase; /* i/o space handle */
#elif defined(__FreeBSD__)
struct kern_devconf *sc_kdc; /* freebsd cruft */
#endif
struct arpcom sc_ac;
#define sc_if sc_ac.ac_if
pdq_t *sc_pdq;
#if defined(__alpha__) || defined(__i386__)
#if !defined(__NetBSD__)
pdq_bus_ioport_t sc_iobase;
#endif
#ifdef PDQ_IOMAPPED
#define sc_membase sc_iobase
#else
pdq_bus_memaddr_t sc_membase;
#endif
pdq_bus_t sc_bc;
#endif /* ! __NetBSD__ */
#if !defined(__bsdi__) || _BSDI_VERSION >= 199401
#define sc_bpf sc_if.if_bpf
#else