Commit Graph

2189 Commits

Author SHA1 Message Date
thorpej 6926d0d4b1 Hand-tuned pmap_zero_page(). 1999-12-17 07:24:05 +00:00
thorpej a07b7d60e2 Garbage-collect. 1999-12-16 20:20:11 +00:00
thorpej 81f44f09a5 - Remove a misguided attempt to use procs as idle contexts for secondary
processors.  Instead, allocate separate idle PCBs for them (including
  the primary -- don't use proc0's for its idle context).
- Use SysValue to store the cpu_info for each processor.
1999-12-16 20:17:22 +00:00
thorpej a5b316c4d5 Key off NSIO and NPCEB for (E)ISA interrupt support.
XXX Can probably nuke the SIO test; don't all of the Noritake-class systems
XXX have EISA?
1999-12-15 22:31:04 +00:00
thorpej 4f580f447c Key off NSIO and NPCEB for (E)ISA interrupt support.
XXX Can probably nuke the SIO test; don't all of the Mikasa-class systems
XXX have EISA?
1999-12-15 22:30:40 +00:00
thorpej 58a51e3b72 Key off NSIO and NPCEB for (E)ISA interrupt support.
XXX Can probably nuke the SIO test; don't all of the ALCOR-class systems
XXX have EISA?
1999-12-15 22:28:15 +00:00
thorpej c557690acc Key off NSIO and NPCEB for (E)ISA interrupt support.
XXX Can probably nuke the SIO test; don't all of the Rawhide-class systems
XXX have EISA?
1999-12-15 22:25:21 +00:00
thorpej 3ffe65b597 Use alpha_shared_intr_{get,set}_private(). 1999-12-15 22:21:45 +00:00
thorpej deed2b3b4b Fix a botch in stray interrupt reporting; report the kn300 IRQ, not the
interrupt enable bit on the MCPCIA the interrupt is mapped to.
1999-12-15 20:10:04 +00:00
thorpej 8b34a5b689 Revert previous. 1999-12-08 23:54:55 +00:00
thorpej fd6f6e85b2 Slight changes so that bounce buffers can be implemented for the Jensen. 1999-12-08 23:40:35 +00:00
thorpej 781149bb12 Handle the case where PCI dense memory and PCI sparse memory don't
overlap; don't require allocation from the dense extent if the PCI
memory address isn't mapped into dense space.

Also, make sure to return an error if a liner mapping is requested
and dense space is not available (not just not requested).
1999-12-08 01:48:39 +00:00
thorpej 9beb275ae8 Oops, committed the wrong version of this file previously. 1999-12-08 00:35:43 +00:00
thorpej a4f30c3f19 Add entry for AlphaServer 2100 (Sable, Sable-Gamma). 1999-12-07 21:51:53 +00:00
thorpej fcf35a8417 Add options, files, etc. for the AlphaServer 2100 (Sable, Sable-Gamma).
Actual source files not yet committed.  Very Soon.
1999-12-07 21:47:12 +00:00
thorpej 25a665e643 Avoid a spurious warning when establishing a pulsed interrupt handler
on an IRQ which was marked "initially-pulsed".
1999-12-07 21:36:16 +00:00
thorpej 4056ebc587 When doing a badaddr check, insert an extra `mb', which is highly magic
on some systems (due to quirky bus adapters).
1999-12-07 21:35:06 +00:00
thorpej ac20942bc5 Some systems don't have dense space; don't require it. 1999-12-07 07:04:39 +00:00
thorpej 51f4c69ad4 Clarify what appear to the untrained eye to be two magic constants (the
address shift and access size shift), and allow them to be overridden
by chip-specific code, if necessary.
1999-12-07 05:44:57 +00:00
drochner 0893832078 update for changed struct wsdisplay_accessops:show_screen signature.
no functional changes
1999-12-06 19:25:56 +00:00
ragge 0513268399 CL* discarding. 1999-12-04 21:13:19 +00:00
mjacob d5e85e61cf Fixes PR#8836. Some changes made by somebody else were a tad incomplete so
configuring w/o SIO broke compilation. I forget why, but there was at one
point (and may still be) a dependency between SIO and EISA. This change
just makes things compile sensibly again. It may make no sense to build
a kernel w/o sio in this case. I can't test this conveniently because I
haven't got a 4100 with a video card in it at the moment.
1999-12-04 20:29:02 +00:00
thorpej 08d1d1b378 Actually, the 2100_A500 has 64 interrupts, not 16. 1999-12-04 00:22:54 +00:00
lukem a63bfb3c6a add atomic.h (missed by thorpej; approved by thorpej) 1999-12-04 00:18:15 +00:00
thorpej 4560ac465a Split the PC-like keyboard controller driver into chip back-end and
bus front-end.
1999-12-03 22:48:22 +00:00
thorpej 0aa48d5c55 New delay(), more carefully coded:
- Use explicit assembly; don't want the compiler optimizing things too
  much here.
- Subtract 2 for each iteration of the loop, rather than 3.  The loop
  consists of only 2 instructions (even the C version compiled to a
  loop of 2 instructions).

The latter change has squashed a fairly annoying timing bug in the
mii_bitbang module as used by the `ex' driver on my AlphaStation 500.

XXX delay() should maybe be rewritten again, to use the rpcc instruction.
1999-12-03 07:29:57 +00:00
thorpej fafcf62fd6 Update my main Alpha development machine's kernel config file to
reflect current reality.
1999-12-03 07:03:43 +00:00
thorpej a51be1961c lock_machdep.c is gone. 1999-12-03 01:13:51 +00:00
thorpej 5d0a62da53 Remove now-obsolete atomic operations. 1999-12-03 01:13:17 +00:00
thorpej 2d8ef60c51 This file is obsolete. 1999-12-03 01:12:00 +00:00
thorpej 2a97466824 Rewrite the atomic locking primitives using in-line assembly. 1999-12-03 01:11:34 +00:00
thorpej d89260177d In pmap_page_protect(), don't reference a pmap we're unlocking via
the PV entry we just freed (D'OH!)
1999-12-02 23:40:27 +00:00
thorpej 9f7d189f05 Inline most of the remaining PALcode calls. 1999-12-02 22:08:04 +00:00
thorpej 90bc415584 Pull in the BWX inlines. We expect the arch to be set appropriately for
the assembler before these files are pulled in by the chip-sepecific files.
1999-12-02 19:44:49 +00:00
thorpej 4e08cc6996 CIA core logic with BWX enabled appears on EV6. We require at least
EV56 for the assembler to emit BWX opcodes, so set the arch to "ev6".
1999-12-02 19:43:58 +00:00
thorpej dc362cf369 CIA core logic with BWX enabled appears on both EV56 and PCA56. We
require at least EV56 for the assembler to emit BWX opcodes, so set
the arch to "ev56".
1999-12-02 19:43:25 +00:00
thorpej 0a2ea99c42 Inline the BWX instructions. 1999-12-02 19:41:39 +00:00
thorpej 4106b60175 Move atomic operations into <machine/atomic.h>, and make them in-line
assembly, rather than function calls.

...except alpha_atomic_testset_l(), which will go away completely once
I commit the new <machine/lock.h>.
1999-12-02 01:09:11 +00:00
thorpej c258dfae2f After reading the GCC `documentation' a little more, improve the inline
__asm() statements added previously for PALcode operations.
1999-12-01 18:23:11 +00:00
thorpej 12f7832ebc don't need private `imb' inline anymore. 1999-11-30 22:32:08 +00:00
thorpej 9314d7f4d7 Use ptoa() consistently when printing out how much memory we have, etc. 1999-11-30 19:31:56 +00:00
thorpej 69b252dfff Put some (disabled) debugging code into pmap_steal_memory(). 1999-11-30 18:18:02 +00:00
thorpej 89ae0bf93c Inline several things from pal.s:
- alpha_rpcc(), alpha_mb(), alpha_wmb() -- these are instructions, and
  we win by inlining them: rpcc is generally used for profiling, and
  the memory barriers really should execute as quickly as possible with
  minimal side-effects (like additional loads/stores required to call the
  functions!)
- alpha_pal_imb(), alpha_pal_rdps(), alpha_pal_swpipl(), alpha_pal_tbi(),
  alpha_pal_whami() -- these are PALcode ops.  We must specify some register
  clobbers for these.

We have a very decent size savings as a result.  My test system:
text    data    bss     dec     hex     filename
2671724 235848  377016  3284588 321e6c  /netbsd.bak
2617708 235736  377016  3230460 314afc  /netbsd

Most of this comes from fewer register saves/restores around spl*() calls
(now that alpha_pal_rdps() and alpha_pal_swpipl() are inlined).

Note that alpha_pal_rdps() and alpha_pal_swpipl() remain in pal.s to
maintain binary compatibility with LKMs that may use spl*() functions.
1999-11-30 00:42:46 +00:00
thorpej 871b54b6d2 Vector to a local function for the IMB IPI. 1999-11-30 00:26:55 +00:00
thorpej 18e6d486f4 Add an IPI which causes the target CPU to perform AST processing when
it returns to userspace.
1999-11-29 20:00:04 +00:00
thorpej 7f1ccd57ea Add a way to get/set a private pointer in the shared interrupt header. 1999-11-29 19:59:19 +00:00
thorpej df2cf70865 - Fix a botch in the IPI bitmasks (they were right-shifted by 1), and
add an IPI which causes the target CPU to perform AST processing when
  it returns to userspace.
- Add a way to get/set a private pointer in the shared interrupt header.
1999-11-29 19:58:39 +00:00
thorpej 68fb3dc662 Switch to the new pmap_remove() and nuke the old one. A simple fork/exit
benchmark shows at least a 10% improvement in the tearing down of a large
address space.
1999-11-29 18:37:28 +00:00
thorpej 94552ad5d6 - Use alpha_atomic_{add,sub}_q() to update the pmap statistics. We now no
longer need to lock the kernel pmap in pmap_kenter_pa() and pmap_kremove().
- Since locking the kernel pmap in interrupt context is no longer required,
  don't go to splimp() when locking the kernel pmap.
- Implement a new pmap_remove() function, not yet enabled by default.  It
  is structured like pmap_protect, and should be *much* faster.  This was
  actually written quite some time ago, but never committed because it
  didn't work properly.  Given the recent bugfix to pmap_protect(), "duh,
  of course it didn't work properly before...".  It seems to work fine now
  (have done several builds and run the UVM regression tests using the new
  code), but it is currently run-time optional so that some performance
  measurements can be easily run against the old and new code.
1999-11-28 19:53:11 +00:00
thorpej 1710fad449 Implement atomic addition and subtraction on quadwords. 1999-11-28 19:47:13 +00:00