table is handled the podulebus mappings are now done at initarm, rather
than in the podulebus code. While I'm not happy with this it does work,
perhaps there's a better way to do it?
Not enableing by default I've not got enough cards to check the podulebus
change hasn't broken something (works with my rapide and with my network
podule)
at run time. This simplifies the code and avoids problems with uninitialised
variables, and if it's good enough for pciide(4), it's good enough for me.
Also normalise the prefix for channel-specific messages.
necessary to allow the card to be detected afterwards. In theory, this
shouldn't be necessary, since we don't touch the page latch yet, but I'm not
going to argue.
SCSIPI_ADAPT_POLL_ONLY to tell the MI scsipi layer to do it for us. This,
plus G/Cing some debugging code, removes the card-specific scsi_request
wrappers.
assigned by RISCOS Ltd (and were assigned by Acorn) to be unique across all
manufacturers. This means that associating each one with a manufacturer (and
checking the manufacturer when attaching) is bogus. Thus, we don't do that
any more.
This should have the pleasant side-effect of getting APDL IDE interfaces
working, since they're just ICS ones with a different manufacturer ID.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in
arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c
podulebussubmatch(), podulechunkdirectory() and podulesncan().
Fix argument types of podulebussubmatch().
Remove podloader_read_region(), since it's not used externally.
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:
icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range
dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range
idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range
Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.
The IOMD/VIDC combination is now moved to arch/arm/iomd together. These
files still need a lot of cleaning up :( .... esp. the RC7500 support that
is still dormant in it; this needs either to be removed or split out for
RC7500's ``VIDC'' video/audio variant.
Apart from the RC7500 support wich is still in arch/arm32 the
iomd,vidc,riscpc and podulebus subdirectories of arch/arm32 can be removed.
This split still uses some small parts of arch/arm32 .... those are the MI
parts that haven't been moved yet.
RiscPC/A7000 have been tested and confirmed to build as should NC.
