NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.
V3 PBC, and use them in the bus mem tag and the bus dma tag on the
P-4032. This allows us to get much further when PMON has configured
the PBC using the old-style PCI address map.
- Compute the number of CPU pipeline cycles per second using the
mc146818.
- Use the COMPARE interrupt for the hardclock interrupt.
- Collapse all interrupt priorities into a single priority, and use
the CPU interrupt inputs to determine the interrupt source (local
device, PCI device, ISA device, etc.)
This allows us to have interrupt sharing.
untested, since I have no P-4032 board, but it's no worse than
the current situation, which is "totally non-working P-4032
support in the ARC port, of all places".
support the P-5064, which has a QED RM5xxx CPU soldered on.
There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU). There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).
There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.
Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.
