non-cached. XXX clean this up by looking at the "non-cacheable" bit of
the full physical address.
avoid having 'nbuf' change between calls to `mdallocsys()' by setting it
in mdallocsys() like the MI allocsys() does. XXX fix this too!
fix some printf lossage.
update for probeget() changes -- though bus_space_probe() appears to be
unused on the sparc64.
device declaration, we don't want it). pull in psycho, pci,
ata and pciide code. clock, eeprom and power attach at sbus
*and* ebus now (clock as `eeprom' works). add `lpt at ebus',
wd major number, and other misc. commented devices.
(`SUNW,sabre') for now, and it doesn't really quite work there yet anyway.
the bus space/dma code is cloned from the sbus driver. the IOMMU code also
is cloned from the sbus code, but separated out into iommu.c so that we can
share it with the sbus driver. hopefully, much of the bus space/dma code
can also be re-shared with the sbus driver and the ebus driver but for now
these copies will do.
support for the real UltraSPARC PCI (`SUNW,psycho') is unwritten, though
most of this code is shared with it.
we can probe PCI config space and try to configue devices, but interrupts
don't work yet...
the bus space/dma code is cloned from the PCI code to do the same thing
which itself was cloned from the sbus bus space/dma code. the bus dma
code is non-functional at this point.
bytes/sector correctly.
Submitted by Detlev Würkner in PR 7653.
Non-trivial merge with the 1.30 change (handle old AmigaDOS fs partitions
with simulated sectorsperblock > 1) by myself, so don't blame Detlev if it
doesn't work (but I checked!).
XXX We still need changes to the file systems to handle this fully.
at levels 5 (sound) and 6 (via1) on the Q700.
Raise splhigh when reading and writing registers. It's ugly, but it's
possible that we could get an interrupt from a higher-level source,
causing a re-read of a memory location.
This is not good when, e.g., we are reading the interrupt register.
Ideally, we would just raise splhigh() in ncr53c9x_readregs(), but
that's m.i. code, and it may be expensive on other architectures.