Commit Graph

1308 Commits

Author SHA1 Message Date
thorpej f818766afe Declare all cfattach structures const. 2002-09-27 20:31:45 +00:00
provos 0f09ed48a5 remove trailing \n in panic(). approved perry. 2002-09-27 15:35:29 +00:00
thorpej 6c88de3b53 Introduce a new routine, config_match(), which invokes the
cfattach->ca_match function in behalf of the caller.  Use it
rather than invoking cfattach->ca_match directly.
2002-09-27 03:17:40 +00:00
thorpej d1ad2ac4f2 Rather than referencing the cfdriver directly in the cfdata entries,
instead use a string naming the driver.  The cfdriver is then looked
up in a list which is built at run-time.
2002-09-27 02:24:06 +00:00
thorpej 274c086b22 Remove <sys/map.h> 2002-09-26 18:54:30 +00:00
simonb 63096043b3 Use "#define\t" instead of "#define ". 2002-09-22 08:30:56 +00:00
chs c081614ea2 it really helps to get the stub right before cutting + pasting it 27 times.
alas, I did not.  doh.
2002-09-22 07:53:39 +00:00
chs 55e1f79335 add pmap_remove_all() hook (empty on most platforms so far). 2002-09-22 07:17:08 +00:00
gmcgarry 45d41256f3 Update for cpu_switch() prototype change. No functional change. 2002-09-22 05:40:35 +00:00
gmcgarry dca80f08fd Add __HAVE_MD_RUNQUEUE flag for MD code to override MI run queue primitives. 2002-09-22 04:11:32 +00:00
manu 80ee637534 - Introduce a e_fault field in struct proc to provide emulation specific
memory fault handler. IRIX uses irix_vm_fault, and all other emulation
use NULL, which means to use uvm_fault.

- While we are there, explicitely set to NULL the uninitialized fields in
struct emul: e_fault and e_sysctl on most ports

- e_fault is used by the trap handler, for now only on mips. In order to avoid
intrusive modifications in UVM, the function pointed by e_fault does not
has exactly the same protoype as uvm_fault:
int uvm_fault __P((struct vm_map *, vaddr_t, vm_fault_t, vm_prot_t));
int e_fault __P((struct proc *, vaddr_t, vm_fault_t, vm_prot_t));

- In IRIX share groups, all the VM space is shared, except one page.
This bounds us to have different VM spaces and synchronize modifications
to the VM space accross share group members. We need an IRIX specific hook
to the page fault handler in order to propagate VM space modifications
caused by page faults.
2002-09-21 21:14:54 +00:00
ragge b3abfee038 Do not include <sys/clist.h>, it's not used in NetBSD at all. 2002-09-19 10:37:59 +00:00
gmcgarry a2e5c0f036 Bring down from nathanw_sa branch. 2002-09-16 07:00:43 +00:00
simonb 7f4e82e47b Add CPU_MIPS_DOUBLE_COUNT for the TX49xx cpus. 2002-09-13 01:27:46 +00:00
simonb f41231cffc Fix the order of the CPU revision and company options fields in the cpu
table for the Alchemy CPUs; successfully recognises an Au1500 now.
2002-09-09 03:42:04 +00:00
simonb 54ef88d289 In the idle functions, set curproc to NULL and (#ifdef LOCKDEBUG) call
sched_unlock_idle before enabling interrupts.  LOCKDEBUG kernels now
boot successfully.

Thanks to Chris Gilbert for helping fix this.
2002-09-09 02:32:38 +00:00
simonb 378a5c4c85 Include "opt_lockdebug.h" here to #ifdef LOCKDEBUG actually does something. 2002-09-09 01:03:10 +00:00
gehenna 77a6b82b27 Merge the gehenna-devsw branch into the trunk.
This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

	device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
  by using this grammer.

- Added the new naming convention.
  The name of the device switch must be <prefix>_[bc]devsw for auto-generation
  of device switch tables.

- The backward compatibility of loading block/character device
  switch by LKM framework is broken. This is necessary to convert
  from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
  We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
  the LKM framework will refer it to assign device major number dynamically.
2002-09-06 13:18:43 +00:00
gmcgarry 1a8058823b RAS support for MIPS. Tested on R3000. 2002-08-28 08:34:06 +00:00
simonb 993a94e6bc Add the Toshiba TX4927 CPU. 2002-08-28 02:09:29 +00:00
simonb 0702d44ac5 Fix printf format string for the EXTENT_DEBUG case. 2002-08-19 12:03:48 +00:00
simonb 771cbe3e84 Remove CPU_MIPS_DOUBLE_COUNT for the MIPS 20Kc - it's cycle counter runs
at the normel CPU frequency.
2002-08-19 12:03:04 +00:00
simonb 7e0228bbc3 Update to rev 1.48 from Algorithmics; adds BONITO64 register definitions. 2002-08-18 16:00:33 +00:00
simonb fd2320f396 Issue a dummy read after a write to the BONITO_PCIMAP_CFG register to
make sure the write is posted; needed to keep the BONITO64 happy.
2002-08-18 15:57:55 +00:00
briggs 0b956d0b8b Implement pmc(9) -- An interface to hardware performance monitoring
counters.  These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface.  Initially, the Intel XScale
counters are the only ones supported.
2002-08-07 05:14:47 +00:00
shin b0d22e8404 fix CPU_ROOT_DEVICE implementation. 2002-08-06 06:54:36 +00:00
shin a59d490375 * add CPU_MIPS_NO_LLSC to Toshiba TX3912, TX3922, TX3927.
* fix mips_has_llsc calculation logic.
2002-08-05 13:02:40 +00:00
shin 2f33f11745 ++CPU_MAXID for CPU_LLSC. 2002-08-05 13:00:47 +00:00
simonb f068458085 The TX79 core in the R5900 doesn't support LL/SC.
XXX: Others in this table will need to be updated.
2002-08-05 02:18:43 +00:00
simonb fef76c7e26 Use a __HAVE_BOOTINFO_H define to check for bootinfo support instead of
speading port names in arch-dependant code.
2002-08-05 02:13:14 +00:00
gmcgarry 460c8c3adc mipsco and sgimips also implement bootinfo, but didn't provide
the CPU_BOOTED_KERNEL sysctl variable.
2002-08-04 03:16:19 +00:00
gmcgarry 7470337484 Move LLSC feature test for mips1 to cputab[]. 2002-08-04 02:27:51 +00:00
gmcgarry 617f58fb55 Add sysctl variable to represent native CPU support for LL/SC instructions. 2002-08-04 01:47:15 +00:00
gmcgarry 886e32d355 mips1 doesn't have native LL/SC instructions. 2002-08-04 01:43:03 +00:00
gmcgarry 3647e0d293 Merge cpu_sysctl() for all mips ports, based on powerpc and m68k precedent.
For now, only pmax implements CPU_BOOTED_KERNEL.  Need to revisit.
2002-08-04 01:41:23 +00:00
simonb e5a27ab142 Sync bcm1250 headers with cfe-1.0.32. 2002-07-31 06:26:24 +00:00
simonb e9dfdd9b2e Add support for the watchdog timers on the BCM1xxx parts. 2002-07-31 05:30:20 +00:00
simonb 314a0f00d1 Fix the mask for the watchdog init and count registers. 2002-07-30 23:10:04 +00:00
simonb c38f2b0214 Remove some debug code accidently left in. 2002-07-29 16:25:02 +00:00
simonb 223e50d28e Add a slightly modified dev/ic/com.c that supports the Alchemy
Semiconductor Au1x00 series on-chip UARTs.  Will be merged with
the original com.c driver once a few issues are tidied up.  Main
differences from a standard 16550 UART are:
 - separate rxdata and txdata registers
 - single 16-bit register for the clock divisor
 - "enable uart" register
2002-07-29 15:42:41 +00:00
simonb ca42af5e80 Add support for the the Alchemy Semiconductor Au1x00 series on-chip
devices.  Currently the serial ports and ethernet MAC have working
drivers, and this has only been physically tested on the Au1000 CPU,
but these devices should work on the Au1100 and Au1500 CPUs too.
2002-07-29 15:39:11 +00:00
itojun f8e5e9c295 be friendly with gcc-3.1.1 -O2, which takes advantage of ANSI C
pointer aliasing rule (gcc optimization/7427).  from tsubai, sync w/kame
2002-07-29 09:14:36 +00:00
simonb 328bb37293 Add support for detecting Alchemy Semiconductor CPUs. Alchemy use the
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.
2002-07-26 00:43:54 +00:00
gmcgarry 2e0c7e68a5 Implement true LL/SC emulation. Mostly from Jason Thorpe in PR17548. 2002-07-21 05:47:51 +00:00
simonb bfbb000051 White space nits, add a #endif comment. 2002-07-19 03:13:55 +00:00
gmcgarry cc4037a913 Overhaul the emulation facility. We do this by:
- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
  and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
  emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.
2002-07-06 23:59:18 +00:00
thorpej 011d4d5f44 Add kernel support for having userland provide the signal trampoline:
* struct sigacts gets a new sigact_sigdesc structure, which has the
  sigaction and the trampoline/version.  Version 0 means "legacy kernel
  provided trampoline".  Other versions are coordinated with machine-
  dependent code in libc.
* sigaction1() grows two more arguments -- the trampoline pointer and
  the trampoline version.
* A new __sigaction_sigtramp() system call is provided to register a
  trampoline along with a signal handler.
* The handler is no longer passed to sensig() functions.  Instead,
  sendsig() looks up the handler by peeking in the sigacts for the
  process getting the signal (since it has to look in there for the
  trampoline anyway).
* Native sendsig() functions now select the appropriate trampoline and
  its arguments based on the trampoline version in the sigacts.

Changes to libc to use the new facility will be checked in later.  Kernel
version not bumped; we will ride the 1.6C bump made recently.
2002-07-04 23:32:02 +00:00
thorpej bf7d5bca07 Eliminate 4 unused sigframe members. 2002-07-04 19:20:01 +00:00
simonb a441a7dffa Remove some clocktick debug code. 2002-06-27 04:09:15 +00:00
simonb 7471732325 Add the 20Kc processor ID. 2002-06-27 03:43:45 +00:00