cache. With secondary cache, the CPU will detect cache coherency errors
and the Virtual Coherency Exception handler will flush the appropriate
cache lines to maintain cache coherency. This allows much better
performance than inhibiting the cache for the entire page. This is
very noticable when shared library mappings occur with incompatible
mappings, since there's a very likely chance the mappings will remain
for long periods of time. Systems without secondary cache will still
have the cache inhibited, so there will still be performance issues if
shared libraries don't get mmaped() on correct memory alignments.
This fixes the current problems on DECstations using the R4x00 getting
coredumped programs.
Support VR4100.
Support 16KB page.
Support CPU without FPU.
Fix virtual alias problem(physio() case).
[new options]
options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
big-endian. i386, pc532 and vax still include <machine/byte_swap.h>
and define macros for the {n,h}to{h,n}*() functions. mips also
defines some endian-independent assembly-code aliases for unaligned
memory accesses.
in kernel mode after master interrupt (MIPS_SR_INT_IE) disabled. Tons
of appreciation for Noriyuki Soda and Masanari Tsubai for almost full
time help to spot of the issue.
- remove "need-flag" for mac68k esp driver, as it is not used in anywhere
and conflicts with IPsec ESP header.
This should be the only MD change in IPv6 support, except kernel config file.
Very sorry if you have any compilation problem with it (I believe it is okay).
If your favorite arch is not included in here, please add a
call to ip6intr() from softintr handle.
either endian. Not a perfect solution which would be revealed on
a certain condition when va_arg() is applied to magical struct
arguments passed by value. format_bytes() is now saved. With the
help from Noriyuki Soda and Masanari Tsubai.
TLBUpdate() routine is used for dual purposes. In TLBmod case, just ok
to call 'tlbwi' (as designed). Result in saving of extraneous execution
path. MIPS1 only this moment.
(correct name, vax?) replacing mips1_TLBFlushAddr and mips1_TLBUpdate,
respectively. New codes always use current ASID holded in EntryHi
register. In most occations, the register already contains a necessary
value before (re-)written, ugh. 'sva | asid' ops for their arguments are
now verbose, to be removed when MIPS3 side changes are done.
'pm_asid' member of 'pmap' structure is assigned a new value after
uvmspace_alloc() provides afresh pmap.
- ASID generation number 0 is not a reserved value anymore.
processor is one of processors with no 'referenced bit' nor 'modified bit'
processor machinary. Those functions are implemented combining two
hardware bits, 'dirty bit' and 'valid bit', with TLBmod exception handler.
per process user spaces, replacing mips1_TBLFlush(). This reserves
kernel space TLB entries when TLBPID generation number about to wrap.
- Correct comments a bit, nuke unused routines.
