I've fixed the problem that's been keeping me from using anything newer than
1.4.1 now. I tracked down the problem checkin, it's the big reorg of
nextdma.c between 1.19 and 1.20. It didn't introduce a new bug but it
activated a check which wasn't activated before. It's the
is-the-limit-in-the-right-window-check which was ifdeffed before because
some DMA-regs would sometimes have strange values. I think I've fixed the
DMA-reg stuff for now: at the end of nextdma_intr, when the csr is poked
to make DMA do something, I think the check for the ENABLE bit introduces a
race condition. I fixed this by unconditionally setting DMACSR_SETENABLE,
this seems to work and also makes the code more readable. I've also tried
setting DMACSR_SETSUPDATE unconditionally and this also works well, but I
don't know what it implies. Unless you have reasons to not set SUPDATE all
the time, I'd suggest making this change as well, it makes the code cleaner
and faster...
I've tested this patch and it does stop the panics, although I don't think setting
SUPDATE all the tima as he suggests is a good idea. The "SUPDATE" bit implies
a single update (i.e. the end of a dma chain.)
"To fully support self-modifying code in any situation, it is imperative that
a CPUSHA intrcution is executed before the execution of the first self-modified
instruction. The CPUSHA instruction has the effect of ensuring that there is
no stale data iin memory, the pipeline is flushed, and instruction prefetches
are repeated and taken from external memory."
I verified that this is the only way (I can think of) to make the sigtramp
regression test work on 68040. doing cpushl dc; cinvl ic; over the affected
address range, then nop (to synchronize the pipeline) is not enough; apparently
the nop does not FLUSH the pipeline and prefetch...
Note that the 68060 UM has copied the above cited passage, but in fact this is
not true. This might be connected to the fact that the 68060 does ensure
memory access order under most conditions.
remove GENERIC.v6 file (as it is part of GENERIC now).
"faith" interface is commented out by default as it is not really for
general use.
IPsec items are commented out as well, though we can enable "options IPSEC"
without export-related issue ("options IPSEC" will enable authentication
portion only). We may need to think about it again.
if you have problem compiling with INET6 on archs I do not have access to,
please contact me.
XXX what to do with arch/arm32/SHARK{,.v6}?
now uses the DMACSR_READ bit and no longer keeps _nd_dmadir in softc
unified transfer cleanup code, now in routine next_dma_finish_xfer()
fixed bounds checking on registers after transfer.
removed checking for bus errors since the bit is always set on some nexts
(specifically, on mourning, a 25mhz 68040 mono slab)
fixed a couple of dma bugs involving chaining dma buffers.
DMACSR_READ is now a CSR status bit which can be used to know if current transfer is
from cpu to device.
the old DMACSR_READ bit is renamed DMACSR_SETREAD. This is a control bit that tells
the dma transfer to be from cpu to device.
that is priority is rasied. Add a new spllowersoftclock() to provide the
atomic drop-to-softclock semantics that the old splsoftclock() provided,
and update calls accordingly.
This fixes a problem with using the "rnd" pseudo-device from within
interrupt context to extract random data (e.g. from within the softnet
interrupt) where doing so would incorrectly unblock interrupts (causing
all sorts of lossage).
XXX 4 platforms do not have priority-raising capability: newsmips, sparc,
XXX sparc64, and VAX. This platforms still have this bug until their
XXX spl*() functions are fixed.
tsutsui