of the corresponding 32bit architecture.
Use it for the 64bit items in netbsd32_statvfs so that the structure
doesn't collect 8byte alignment (and 4 bytes of trailing padding).
This replaces the 'packed' attribute which wasn't architecture specific
and would cause massive overheads accessing every member of sparc64.
Should allow the MIPS64 port do DTRT.
from doc/BRANCHES:
idle lwp, and some changes depending on it.
1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
Do not set the DMMU secondary context to 0 (that would be kernel), and
add a few required membars after switching the secondary dmmu context.
This avoids SIRs caused by double kernel_data_faults, caused by spills
of obsolete user windows after the context for that user pmap is gone.
int _bus_dmatag_subregion(bus_dma_tag_t tag,
bus_addr_t min_addr,
bus_addr_t max_addr,
bus_dma_tag_t *newtag,
int flags)
void _bus_dmatag_destroy(bus_dma_tag_t tag)
that allow a (normally broken/limited) device to restrict the bus address
range it can talk to. this is used by bce(4) to limit DMA addresses to
1GB range, the maximum the chip can address.
all this is from Yorick Hardy <yhardy@uj.ac.za> with input from several
people on tech-kern.
XXX: bus_dma(9) needs an update still.
by Slava Semushin <slava.semushin@gmail.com>.
To verify that no nasty side effects of duplicate includes (or their
removal) have an effect here, I've compiled an i386/ALL kernel with
and without the patch, and the only difference in the resulting .o
files was in shifted line numbers in some assert() calls.
The comparison of the .o files was based on the output of "objdump -D".
Thanks to martin@ for the input on testing.
- finish implementing splraiseipl (and makeiplcookie).
http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
- complete workqueue(9) and fix its ipl problem, which is reported
to cause audio skipping.
- fix netbt (at least compilation problems) for some ports.
- fix PR/33218.
stack, cpu_info structure, panicstack, idle uarea and normal kernel
stack in here. the idle uarea and kernel stack are in the 2nd 64KB
page. the interrupt stack and cpu_info structure are as the same
place in the 1st 64KB page, and the panicstack grows down from the
top of this page. update comments in param.h to suit (XXX: a lot
of these constants should move to a header file that will not pollute
the name space so much.) map these pages identically between
cpu_initialise() and cpu_mp_startup(), and deal with the two 64KB
pages in pmap_extract(). keep an unmapped 64KB page between them.
don't initialise the unused "ci_eintstack" member of the cpu_info
structure
use constants to initialise many addresses in the cpu_info structure,
consolidating these assignments from cpu0 and cpu>0
delete u0/estack0/panicstack from locore.s
clean up some wrong comments in locore.s
fix a 32bit-only bug in cpu_mp_startup().
delete 'u0' entirely.
this fixes recent random lossage seen on port-sparc64: processes
stuck in RUN state, data faults, and hangs.
on an Ultra 2 and works fine, apart from formatting which is known
to be broken. It failed to work on an ebus machine. The ebus
support compiles fine, but I don't have hardware for testing. This
code is based on the sparc driver with hints from OpenBSD on how
to do the sbus and ebus attachments, along with help from martin@
and mrg@.
Initial commit approved by martin@
TODO:
- fix ebus support
- fix XXX issues
- check resource deallocation
- fix formatting
- merge remaining differences from sparc driver
- split out back end chip support
- have sparc driver use new common back end chip support
- adapt to newlock when branch is ready
- adapt to "disk-info" property dictionary
and tables to map fimware names to driver names. Based on a suggestion
from Eduardo (quite some time ago).
Each device (on busses we can handle and care about) gets a device property
storing the devices OpenFirmware package handle. To match the boot device,
the phandle of the chosen bootpath is compared against this property,
plus some additional string matching for disk/cd devices (where OF only
provides a node for the device class, not each instance).
is still not working.)
cpu.h:
- add a pointer for DDB regs in SMP environment to struct cpu_info
- remove the #defines for mp_pause_cpus() and mp_resume_cpus()
cpuset.h:
- remove CPUSET_ALL() and rename CPUSET_ALL_BUT() to CPUSET_EXCEPT()
from petrov.
db_machdep.h:
- rename the members of db_regs_t to be the same as sparc
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- redo DDB_REGS to no longer be a pointer to a fixed data structure
but to one allocated per-cpu when ddb is entered
- move a bunch of prototypes in here
intr.h:
- remove SPARC64_IPI_* macros, no longer used
db_interface.c:
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- make "nil" a 64 bit entity
- change the ddb register access methods to work in multiprocessor
environment, it is now very much like sparc does it
- in kdb_trap() avoid accessing ddb_regp when it is NULL
- update several messages to include the cpu number
- unpause other cpus much later when resuming from ddb
- rename db_lock() to db_lock_cmd(), as the sparc-like code has
db_lock as a simple lock
- remove "mach cpus" command, and replace it with "mach cpu" (which
does the same) and also implement "mach cpu N" to switch to
another cpus saved trapframe
db_trace.c:
- update for the ddb_regs -> ddb_regp change
genassym.cf:
- add TF_KSTACK as offsetof(struct trapframe64, tf_kstack)
ipifuncs.c:
- overhaul extensively
- remove all normal interrupt handlers as IPI's, we now handle
them all specially in locore.s:interrupt_vector
- add a simplelock around all ipi functions - it's not safe for
multiple cpus to be sending IPI's to each other right now
- rename sparc64_ipi_pause() to sparc64_ipi_pause_thiscpu() and,
if DDB is configured, enable it to save the passed-in trapframe
to a db_regs_t for this cpu's saved DDB registers.
- remove the "ipimask" system (SPARC64_IPI_* macros) and instead
pass functions directly
- in sparc64_send_ipi() always set the interrupt arguments to 0,
the address and argument of the to be called function. (the
argument right now is the address of ipi_tlb_args variable, and
part of the reason why only one CPU can send IPI's at a time.)
don't wait forever for an IPI to complete. some of this is
from petrov.
- rename sparc64_ipi_{halt,pause,resume}_cpus() to
mp_{halt,pause,resume}_cpus()
- new function mp_cpu_is_paused() used to avoid access missing
saved DDB registers
- actually broadcast the flush in smp_tlb_flush_pte(),
smp_tlb_flush_ctx() and smp_tlb_flush_all(). the other end may
not do anything yet in the pte/ctx cases yet...
kgdb_machdep.c:
- rework for changed member names in db_regs_t.
locore.s:
- shave an instruction from syscall_setup() (set + ld -> sethi + ld)
- remove some old dead debug code
- add new sparc64_ipi_halt IPI entry point, it just calls the C
vector to shutdown.
- add new sparc64_ipi_pause IPI entry point, which just traps into
the debugger using the normal breakpoint trap. these cpus usually
lose the race in db_interface.c:db_suspend_others() and end up
calling the C vector sparc64_ipi_pause_thiscpu().
- add #if 0'ed code to sparc64_ipi_flush_{pte,ctx}() IPI entry
points to call the sp_ version of these functions.
- in rft_kernel (return from trap, kernel), check to see if the
%tpc is at the sparc64_ipi_pause_trap_point and if so, call
"done" not "retry"
- rework cpu_switch slightly: save the passed-in lwp instead of
using the one in curlwp
- in cpu_loadproc(), save the new lwp not the old lwp, to curlwp
- in cpu_initialize(), set %tl to zero as well. from petrov.
- in cpu_exit(), fix a load register confusion. from petrov.
- change some "set" in delay branch to "mov".
machdep.c:
- deal with function renames
pmap.c:
- remove a spurious space
trap.c:
- remove unused "trapstats" variable
- add cpu number to a couple of messages
modifies machine/db_machdep.h: BKPT_SET(inst) to BKPT_SET(inst, addr) for all archs ie; passess the
breakpoint address as well.
Patch from cherry@mahiti.org
- Accept bootinfo structure passed down from ofwboot v1.9
- Drop kernel re-mapping code
- Use permanent 4MB mappings provided by the loader instead
- Change kernel entry address to point directly at the code instead of pointing
at the trap table's first slot. This allows the bootloader to detect
those kernels which are aware of the new boot scheme
- Due to the changes in kernel mapping code, alter secondary CPU bootstrap
code to use trampoline just like FreeBSD does (some FreeBSD code is used
here as well)
