out how much s/g ram is available. Can't really use the 128K entry S/G
ram yet- but I'll fix that later. More importantly, add in a dwlpx_iointr
handler that will try and figure out what the DWLPX error is and at
least print out what is happening- I actually found it useful in S/G
entry debugging as it could tell me that I had some bad S/G entries.
* Add more #ifdef pmax/#endif, #ifdef alpha/#endif where appropriate.
Config and heade files need more work (or replacement)
change TK_NOTYET to HAVE_RCONS
change commented-out /* && cn_tab.cn_screen */ to && raster_console()
* Add DDB hooks.
* Note where Alpha console ignores carrier on consoles.
* Add pmax-derived console tty-size code inside HAVE_RCONS
* Fold in gross pmax rcons-input hooks, inside HAVE_RCONS
Untested, but whitespace/ifdef only, cross-compiles OK,
preprocessing shows no significat differences (famous last words)
the TLB and I-cache in the SWITCH_CONTEXT macro.
- Right after switching to proc0's newly-created context at startup time,
flush the TLB and I-cache; this is the only place where it's not done
automatically.
- Fix a nasty bug in a critical section of cpu_switch(); change the
pmap_activate -> SWITCH_CONTEXT -> pmap_deactivate sequence to
pmap_deactivate -> pmap_activate -> SWITCH_CONTEXT. This prevents
erroneously marking a pmap inactive if switching to a process that
shares it's address space (and thus its pmap) with the oldproc! Noticed
by Chris Demetriou.
of TLB and I-cache flushes, significantly speeding up context switches.
Once again, many thanks to Chris Demetriou and Ross Harvey for code
review and debugging assistance!
invalidation algorithm:
if (old mapping had PG_ASM set || pmap is active) {
TIBS(va);
if (also sync I-stream)
imb();
}
The check for "old mapping had PG_ASM" will get all kernel mappings (since
kernel mappings always have PG_ASM set).
This allows us to remove the bogus check for the kernel pmap in
active_pmap() - do so.
Use the new TLB invalidation macro whenever such action is needed.
as well, until some other changes are made). Nuke active_user_pmap(),
and change the places that used it to use active_pmap() instead (as well
as make some DIAGNOSTIC consistency checks).
the PTE was previously invalid, no TLB invalidation is necessary because:
(1) when a PTE is invalidated, its entry is flushed from the
TLB
(2) the PALcode won't install an invalid PTE into the TLB.
structure. We will continue to run on this context (which is the
global Lev1map at this point) right up until we switch to proc0's
context in switch_exit().
Major change is that page table page management has been completely
rewritten. Page tables are now accessed via K0SEG (no more KVA space
wasted on user page tables), and a much larger user address space is
supported.
Many thanks to Chris Demetriou and Ross Harvey for helpful insight and
debugging assistance.
