pgoyette
85c2855a07
Fix toyp in previous. Pointed out by snj@
2009-05-13 23:26:38 +00:00
pgoyette
1463b8efaf
1. Extend CPU probe of Intel processors to handle extended-models. This
...
allows us to properly identify new Intel 45nm processors, Core i7,
Atom, and the 45nm Xeon MP.
2. Properly decode several new Intel cache descriptors, as listed in the
most recent (March 2009) edition of Intel's Application Note 485.
3. Convert decode of the various features masks to use the newly added
snprintb_m(3) routine.
Addresses my PR bin/41289
Addresses my PR bin/41290
2009-05-13 22:25:51 +00:00
lukem
be3963b646
Constify a userland-only member.
2009-04-15 05:56:36 +00:00
christos
fc39241e29
don't undef __CI_TBL before we use it :-)
2008-05-30 21:53:00 +00:00
christos
6cb1513d20
- fix an amd cache entry.
...
- merge tables
- support phenom
from Paul Goyette
2008-05-30 18:49:03 +00:00
christos
f26920b377
PR/38722: Paul Goyette: Share cacheinfo information
2008-05-30 14:42:42 +00:00
cegger
c094da181a
print L3 and TLB cache information for AMD Barcelona/Phenom
2008-05-11 21:19:17 +00:00
ad
50d8ae9d14
Simplify x86 identcpu code, and share between i386/amd64.
2008-05-11 14:44:53 +00:00
yamt
f141fad5f8
make multi inclusion protection macros consistent.
2005-04-16 07:45:59 +00:00
briggs
4634c8ef35
Get correct cache information for earlier VIA C3 models.
...
Mostly from PR kern/26689 submitted by Michael van Elst.
2004-08-17 15:27:46 +00:00
briggs
bd2376263b
VIA C3 cache info.
2004-08-08 05:16:16 +00:00
fvdl
4b293b5851
Share some common cache info cpuid code between i386 and x86_64.
2003-04-25 21:54:29 +00:00
