160 lines
4.9 KiB
C
160 lines
4.9 KiB
C
/* $NetBSD: cacheinfo.h,v 1.4 2005/04/16 07:45:59 yamt Exp $ */
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#ifndef _X86_CACHEINFO_H_
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#define _X86_CACHEINFO_H_
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struct x86_cache_info {
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uint8_t cai_index;
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uint8_t cai_desc;
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uint8_t cai_associativity;
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u_int cai_totalsize; /* #entries for TLB, bytes for cache */
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u_int cai_linesize; /* or page size for TLB */
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const char *cai_string;
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};
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#define CAI_ITLB 0 /* Instruction TLB (4K pages) */
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#define CAI_ITLB2 1 /* Instruction TLB (2/4M pages) */
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#define CAI_DTLB 2 /* Data TLB (4K pages) */
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#define CAI_DTLB2 3 /* Data TLB (2/4M pages) */
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#define CAI_ICACHE 4 /* Instruction cache */
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#define CAI_DCACHE 5 /* Data cache */
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#define CAI_L2CACHE 6 /* Level 2 cache */
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#define CAI_COUNT 7
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struct cpu_info;
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const struct x86_cache_info *cache_info_lookup(const struct x86_cache_info *,
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u_int8_t);
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void amd_cpu_cacheinfo(struct cpu_info *);
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void via_cpu_cacheinfo(struct cpu_info *);
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void x86_print_cacheinfo(struct cpu_info *);
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/*
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* AMD Cache Info:
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*
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* Athlon, Duron:
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*
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* Function 8000.0005 L1 TLB/Cache Information
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* EAX -- L1 TLB 2/4MB pages
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* EBX -- L1 TLB 4K pages
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* ECX -- L1 D-cache
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* EDX -- L1 I-cache
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*
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* Function 8000.0006 L2 TLB/Cache Information
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* EAX -- L2 TLB 2/4MB pages
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* EBX -- L2 TLB 4K pages
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* ECX -- L2 Unified cache
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* EDX -- reserved
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*
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* K5, K6:
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*
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* Function 8000.0005 L1 TLB/Cache Information
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* EAX -- reserved
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* EBX -- TLB 4K pages
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* ECX -- L1 D-cache
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* EDX -- L1 I-cache
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*
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* K6-III:
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*
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* Function 8000.0006 L2 Cache Information
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* EAX -- reserved
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* EBX -- reserved
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* ECX -- L2 Unified cache
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* EDX -- reserved
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*/
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/* L1 TLB 2/4MB pages */
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#define AMD_L1_EAX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
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#define AMD_L1_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
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#define AMD_L1_EAX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
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#define AMD_L1_EAX_ITLB_ENTRIES(x) ( (x) & 0xff)
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/* L1 TLB 4K pages */
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#define AMD_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
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#define AMD_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
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#define AMD_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
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#define AMD_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff)
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/* L1 Data Cache */
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#define AMD_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define AMD_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff)
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#define AMD_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff)
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#define AMD_L1_ECX_DC_LS(x) ( (x) & 0xff)
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/* L1 Instruction Cache */
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#define AMD_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define AMD_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff)
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#define AMD_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff)
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#define AMD_L1_EDX_IC_LS(x) ( (x) & 0xff)
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/* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */
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/* L2 TLB 2/4MB pages */
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#define AMD_L2_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
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#define AMD_L2_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
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#define AMD_L2_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
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#define AMD_L2_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
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/* L2 TLB 4K pages */
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#define AMD_L2_EBX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
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#define AMD_L2_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
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#define AMD_L2_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
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#define AMD_L2_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
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/* L2 Cache */
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#define AMD_L2_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024)
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#define AMD_L2_ECX_C_ASSOC(x) (((x) >> 12) & 0xf)
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#define AMD_L2_ECX_C_LPT(x) (((x) >> 8) & 0xf)
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#define AMD_L2_ECX_C_LS(x) ( (x) & 0xff)
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/*
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* VIA Cache Info:
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*
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* Nehemiah (at least)
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*
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* Function 8000.0005 L1 TLB/Cache Information
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* EAX -- reserved
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* EBX -- L1 TLB 4K pages
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* ECX -- L1 D-cache
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* EDX -- L1 I-cache
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*
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* Function 8000.0006 L2 Cache Information
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* EAX -- reserved
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* EBX -- reserved
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* ECX -- L2 Unified cache
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* EDX -- reserved
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*/
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/* L1 TLB 4K pages */
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#define VIA_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
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#define VIA_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
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#define VIA_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
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#define VIA_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff)
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/* L1 Data Cache */
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#define VIA_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define VIA_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff)
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#define VIA_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff)
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#define VIA_L1_ECX_DC_LS(x) ( (x) & 0xff)
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/* L1 Instruction Cache */
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#define VIA_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define VIA_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff)
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#define VIA_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff)
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#define VIA_L1_EDX_IC_LS(x) ( (x) & 0xff)
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/* L2 Cache (pre-Nehemiah) */
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#define VIA_L2_ECX_C_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define VIA_L2_ECX_C_ASSOC(x) (((x) >> 16) & 0xff)
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#define VIA_L2_ECX_C_LPT(x) (((x) >> 8) & 0xff)
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#define VIA_L2_ECX_C_LS(x) ( (x) & 0xff)
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/* L2 Cache (Nehemiah and newer) */
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#define VIA_L2N_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024)
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#define VIA_L2N_ECX_C_ASSOC(x) (((x) >> 12) & 0xf)
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#define VIA_L2N_ECX_C_LPT(x) (((x) >> 8) & 0xf)
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#define VIA_L2N_ECX_C_LS(x) ( (x) & 0xff)
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#endif /* _X86_CACHEINFO_H_ */
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