Commit Graph

14 Commits

Author SHA1 Message Date
gavan
f2c2467d5c Correct masks for PCIXSR decomposition 2003-12-19 10:08:11 +00:00
gavan
5232db351e The PIRSR is at location 0xffffe1ec, not 0xffffe2ec.
Source: Intel(R) 80321 I/O Processor Developer's Manual, page 578
2003-12-16 00:04:09 +00:00
thorpej
d322684f55 Add support for the i80312 and i80321 I2C controllers. 2003-10-06 16:06:05 +00:00
thorpej
adef1b7dab Add PBIU register bits. 2003-07-28 16:53:31 +00:00
briggs
87079147ff Add some more register definitions. 2003-02-06 03:01:32 +00:00
thorpej
a264c879c9 Remove the DMA controller register defns from this file (much like
the AAU registers are not in this file) -- iopdma is not specific to
i80321.
2003-02-06 02:01:35 +00:00
briggs
6c79464645 Actually make a bitmask for ICU_INT_HWMASK. 2003-02-06 01:36:07 +00:00
thorpej
21fbbf679c Define a base for each DMA channel. 2003-01-01 00:44:34 +00:00
thorpej
072eedb728 Add a symbolic constant for where external interrupts start. 2002-10-03 20:10:40 +00:00
thorpej
d038c91c0c Delete all the AAU register definitions; they are moved to a separate
file in a future commit.
2002-08-02 00:33:29 +00:00
thorpej
c92ad565ad * Remove some AAU definitions -- they will be defined elsewhere in
a future commit.
* Fix a typo in the watchdog enable names.
* Add SSP (synchronous serial port, for SPI, Microwire, etc.) definitions.
2002-07-29 17:28:06 +00:00
thorpej
f23ba7637c Add Application Accelerator Unit registers. 2002-04-16 17:36:06 +00:00
thorpej
bbdbd9ab37 Add i80321 DMA controller registers. 2002-04-16 04:50:14 +00:00
thorpej
f536211623 Basic support for the Intel i80321 I/O Processor (Xscale core).
Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.
2002-03-27 21:45:47 +00:00