gavan
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f2c2467d5c
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Correct masks for PCIXSR decomposition
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2003-12-19 10:08:11 +00:00 |
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gavan
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5232db351e
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The PIRSR is at location 0xffffe1ec, not 0xffffe2ec.
Source: Intel(R) 80321 I/O Processor Developer's Manual, page 578
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2003-12-16 00:04:09 +00:00 |
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thorpej
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d322684f55
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Add support for the i80312 and i80321 I2C controllers.
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2003-10-06 16:06:05 +00:00 |
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thorpej
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adef1b7dab
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Add PBIU register bits.
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2003-07-28 16:53:31 +00:00 |
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briggs
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87079147ff
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Add some more register definitions.
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2003-02-06 03:01:32 +00:00 |
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thorpej
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a264c879c9
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Remove the DMA controller register defns from this file (much like
the AAU registers are not in this file) -- iopdma is not specific to
i80321.
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2003-02-06 02:01:35 +00:00 |
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briggs
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6c79464645
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Actually make a bitmask for ICU_INT_HWMASK.
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2003-02-06 01:36:07 +00:00 |
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thorpej
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21fbbf679c
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Define a base for each DMA channel.
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2003-01-01 00:44:34 +00:00 |
|
thorpej
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072eedb728
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Add a symbolic constant for where external interrupts start.
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2002-10-03 20:10:40 +00:00 |
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thorpej
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d038c91c0c
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Delete all the AAU register definitions; they are moved to a separate
file in a future commit.
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2002-08-02 00:33:29 +00:00 |
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thorpej
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c92ad565ad
|
* Remove some AAU definitions -- they will be defined elsewhere in
a future commit.
* Fix a typo in the watchdog enable names.
* Add SSP (synchronous serial port, for SPI, Microwire, etc.) definitions.
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2002-07-29 17:28:06 +00:00 |
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thorpej
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f23ba7637c
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Add Application Accelerator Unit registers.
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2002-04-16 17:36:06 +00:00 |
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thorpej
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bbdbd9ab37
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Add i80321 DMA controller registers.
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2002-04-16 04:50:14 +00:00 |
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thorpej
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f536211623
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Basic support for the Intel i80321 I/O Processor (Xscale core).
Note: This is a snapshot of work-in-progress; there are still some
bugs to be shaken out.
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2002-03-27 21:45:47 +00:00 |
|