the address of the desired PTE location is readily available in the
callers context (setpte4m() retraces the entire 3-level structure
to arrive at the PTE location).
Also, in many cases we can do away with the distinction between pmaps
that have or have not allocated a context. This is really only useful
in cases where we're interested in the REF or MOD bits which can differ
in the TLB version of a PTE. By doing this, we avoid getpte()'s which
in many cases instruct the MMU to start a table walk only to find out
that there's nothing there after going 2/3 of the way, or waste a TLB
entry because of TLB flushing soon after getpte() completes.
In addition, there's a hook to flush the cache line corresponding to
the (kernel virtual) location of a PTE entry when it gets altered.
allocate and initialize all kernel page tables before looking at the
PROM maps, which allows mmu_reservemon4m() to simply walk the PROM tables
without having to allocate bits and pieces of our own kernel tables.
Slightly optimize getcontext() macros in mutli-arch kernels.
Remove un-needed `4m' version of mmu_pagein().
Some of the stuff (e.g., rarpd, bootpd, dhcpd etc., libsa) still will
only support Ethernet. Tcpdump itself should be ok, but libpcap needs
lot of work.
For the detailed change history, look at the commit log entries for
the is-newarp branch.
fault-status reading stubs pre-cook the arguments.
illegal instruction trap: catch iflush instructions that cause this trap
on some CPU/MMU combinations.
Call get_cpuinfo() for the boot CPU to collect the minimum information
to get the bootstrap rolling.
sun4/sun4c: the Interrupt Enable register is now mapped here after pmap
is initialized (was in locore).
Replace `cpumod' and `mmumod' with `cpuinfo.*' equivalents.
Allow more than one CPU to be configured in mainbus_attach().
Many things in here were imported from an earlier version from Aaron
Brown and are not yet used. This version has all the attributes of a
snapshot; more to come as addtional CPU/MMU details get implemented.
Use a table driven classification based on CPU and MMU implementation/version
fields. Each CPU class or module defines a collection of routines that
implement CPU or MMU specific operations that can collect detailed setup
information.
All information is collected in a `cpu_softc' structure provided by the
auto-configuration code. However, in the interest of SMP support this
structure is located at a fixed virtual address identified by the
symbol `cpuinfo'. The `boot' CPU currently uses the the physical page(s) at
address 0x2000 for its cpuinfo. Consequently, the fixed virtual address
will be `KERNBASE+0x2000'.
The cache flush routines for several systems (sun4/4c vs. sun4m;
virtual vs. physical tags) have been factored out. Function pointers
to an appropriate set are located in `cpuinfo'. The former global
`cacheinfo' structure is now also a part of `cpuinfo'. Because of the
fixed virtual address of `cpuinfo' no extra performance penalties
are incurred by this move. In multi-architecture kernels, there's
no longer the need for run-time `cputyp' tests in this part of the system.
some at startup depending on architecture.
Use `get_faultstatus' field in `cpuinfo' (initialized in cpu.c) to branch
to CPU/MMU specific fault status reading stubs on memory fault traps.
Remove code top map the Interrupt Enable register on sun4/sun4c. Its VA
has moved to a high location and is now mapped in autoconf.c after
pmap has initialized. Note: this renders NMIs during bootstrap() fatal
(maybe loading %tbr should be deferred).
pk