- Change structures for each device to make them more suitable with
our scsipi mid-layer.
- Use ADAPTER_REQ_SET_XFER_MODE callback.
- Cleanup misc functions/structures/style.
XXX Tagged queuieng support is disabled for now.
XXX Maybe we should have common library of the scsi protocol engine
XXX to share it among all other drivers..
dependent files:
- Use infrastructure from distrib/common to build file system images with
crunchgen-ed programs from a list file.
- Non root ("UNPRIVED") builds from a read-only source tree are possible,
as makefs(8) replaces vnconfig(8)/vnd use, devices are generated using
common/makedev2spec.awk, etc.
- Cross builds should be possible, except that some ports need cross-compile
host tool versions of installboot and any appropriate host disk labelling
tools.
XXX: pmax, sparc and vax need fixing for this!
- This code has NOT YET BEEN TESTED on most of the ports.
It should work, but it is extremely likely that the file system
parameters may need tweaking to get things to fit.
See MAKEFS_FLAGS in sparc/miniroot/Makefile.inc for an example.
If assistance is required, please ask!
sequence using the reciprocal of the delay divisor to perform the
division.
Set the cp0 compare register so that it doesn't trigger interrupts and
reset the cp0 count register in the hardclock interrupt handler.
To implement a more accurate microtime using the CP0 COUNT
register we need to divide that register by the number of
cycles per MHz. But...
DIV and DIVU are expensive on MIPS (eg 75 clocks on the
R4000). MULT and MULTU are only 12 clocks on the same CPU.
On the SB1 these appear to be 40-72 clocks for DIV/DIVU and 3
clocks for MUL/MULTU.
The strategy we use to to calculate the reciprical of cycles
per MHz, scaled by 1<<32. Then we can simply issue a MULTU
and pluck of the HI register and have the results of the
division.
"swarm"). Other SB-cpu boards will be supported by this port in
the future.
Includes support for on-chip ethernet and serial. Many features
still missing - notably SMP, PCI/LDT and IDE.
This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
wiz