process context ('reaper').
From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
as FPU state), and is the last potentially blocking operation;
all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
for both 'process' and 'lwp' exit
uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.
MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.
g/c now unneeded routines and variables, including the reaper kernel thread
virtual memory reservation and a private pool of memory pages -- by a scheme
based on memory pools.
This allows better utilization of memory because buffers can now be allocated
with a granularity finer than the system's native page size (useful for
filesystems with e.g. 1k or 2k fragment sizes). It also avoids fragmentation
of virtual to physical memory mappings (due to the former fixed virtual
address reservation) resulting in better utilization of MMU resources on some
platforms. Finally, the scheme is more flexible by allowing run-time decisions
on the amount of memory to be used for buffers.
On the other hand, the effectiveness of the LRU queue for buffer recycling
may be somewhat reduced compared to the traditional method since, due to the
nature of the pool based memory allocation, the actual least recently used
buffer may release its memory to a pool different from the one needed by a
newly allocated buffer. However, this effect will kick in only if the
system is under memory pressure.
superfluous by Tsutsui-san's previous changes.
(this change differs slightly from that posted to port-mips@, as
mips_flushcache_allpvh should be compiled iff MIPS3_PLUS is defined and
MIPS3_L2CACHE_ABSENT should be removed from files.mips as well)
Gone are the old kern_sysctl(), cpu_sysctl(), hw_sysctl(),
vfs_sysctl(), etc, routines, along with sysctl_int() et al. Now all
nodes are registered with the tree, and nodes can be added (or
removed) easily, and I/O to and from the tree is handled generically.
Since the nodes are registered with the tree, the mapping from name to
number (and back again) can now be discovered, instead of having to be
hard coded. Adding new nodes to the tree is likewise much simpler --
the new infrastructure handles almost all the work for simple types,
and just about anything else can be done with a small helper function.
All existing nodes are where they were before (numerically speaking),
so all existing consumers of sysctl information should notice no
difference.
PS - I'm sorry, but there's a distinct lack of documentation at the
moment. I'm working on sysctl(3/8/9) right now, and I promise to
watch out for buses.
rename FPBASE to _FPBASE, so that we avoid polluting the user's
name space when e.g. <sys/ptrace.h> is included. Previously, the
PC symbol in mips/regnum.h would conflict with the declaration of
the external variable by the same name in termcap.h, as discovered
by the ``okheaders'' regression test.
Remove p_raslock and rename p_lwplock p_lock (one lock is enough).
Simplify window test when adding a ras and correct test on VM_MAXUSER_ADDRESS.
Avoid unpredictable branch in i386 locore.S
(pad fields left in struct proc to avoid kernel bump)
1) R10k uses VA0 to select cache ways, but in rev. 1.1, VA14
is used instead.
2) R10k does not support HitWriteBack and should map HitWriteBack
to HitWriteBackInvalidate, but in rev. 1.1, HitWriteBack is not
handled properly.
So, cache_r10k.c rev. 1.1 was replaced by new implementation.
containing signal posting, kernel-exit handling and sa_upcall processing.
XXX the pc532, sparc, sparc64 and vax ports should have their
XXX userret() code rearranged to use this.
the MI i2c "strtc" device.
XXX: This should use the MI "strtc" device - the M41T81 should be
compatible enough with the M41ST84 currently supported by that
driver.
a copy of the interrupt cookie which isn't used outside the attach. We
has also bogusly only told the autoconfiguration machinery that our softc
was as big as a ohci_softc_t, not a struct aubus_ohci_softc.
Also, disestablish the interrupt if OHCI initialisation fails.
R10000 L2 cache (which is 2-way set-associative write-back),
so use r4k_sdcache_wbinv_range_NN() for workaround until someone
implement proper r10k_sdcache_*() ops.
Problem reported by Christopher SEKIYA.
