Remove preprocessor conditional MIPS3_L2CACHE_ABSENT, which was rendered
superfluous by Tsutsui-san's previous changes. (this change differs slightly from that posted to port-mips@, as mips_flushcache_allpvh should be compiled iff MIPS3_PLUS is defined and MIPS3_L2CACHE_ABSENT should be removed from files.mips as well)
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@ -1,4 +1,4 @@
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# $NetBSD: files.mips,v 1.48 2003/10/29 23:41:49 christos Exp $
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# $NetBSD: files.mips,v 1.49 2003/12/12 14:55:58 sekiya Exp $
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#
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defflag opt_cputype.h NOFPU
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@ -11,8 +11,7 @@ defflag opt_cputype.h NOFPU
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# ENABLE_MIPS_TX3900
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# ENABLE_MIPS_R4700
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# ENABLE_MIPS_R3NKK
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defflag opt_mips_cache.h MIPS3_L2CACHE_ABSENT
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MIPS3_NO_PV_UNCACHED
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defflag opt_mips_cache.h MIPS3_NO_PV_UNCACHED
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ENABLE_MIPS4_CACHE_R10K
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file arch/mips/mips/locore_mips1.S mips1
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.153 2003/11/01 14:48:16 tsutsui Exp $ */
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/* $NetBSD: pmap.c,v 1.154 2003/12/12 14:55:58 sekiya Exp $ */
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/*-
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* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
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@ -74,7 +74,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.153 2003/11/01 14:48:16 tsutsui Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.154 2003/12/12 14:55:58 sekiya Exp $");
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/*
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* Manages physical address maps.
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@ -260,11 +260,10 @@ struct pool_allocator pmap_pv_page_allocator = {
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* Misc. functions.
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*/
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#ifdef MIPS3_PLUS /* XXX mmu XXX */
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#if defined(MIPS3_PLUS) /* XXX mmu XXX */
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void mips_dump_segtab(struct proc *);
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#endif
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static void mips_flushcache_allpvh(paddr_t);
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#if defined(MIPS3_L2CACHE_ABSENT)
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/*
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* Flush virtual addresses associated with a given physical address
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*/
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@ -288,7 +287,7 @@ mips_flushcache_allpvh(paddr_t pa)
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}
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#endif
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}
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#endif /* MIPS3_L2CACHE_ABSENT */
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#endif /* MIPS3_PLUS */
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/*
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* Bootstrap the system enough to run with virtual memory.
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@ -1583,7 +1582,7 @@ pmap_zero_page(phys)
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mips_pagezero((caddr_t)MIPS_PHYS_TO_KSEG0(phys));
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#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
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#if defined(MIPS3_PLUS) /* XXX mmu XXX */
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/*
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* If we have a virtually-indexed, physically-tagged WB cache,
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* and no L2 cache to warn of aliased mappings, we must force a
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@ -1595,7 +1594,7 @@ pmap_zero_page(phys)
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*/
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if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0)
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
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#endif /* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
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#endif /* MIPS3_PLUS */
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}
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/*
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@ -1616,7 +1615,7 @@ pmap_copy_page(src, dst)
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printf("pmap_copy_page(%lx) dst nonphys\n", (u_long)dst);
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#endif
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#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
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#if defined(MIPS3_PLUS) /* XXX mmu XXX */
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/*
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* If we have a virtually-indexed, physically-tagged cache,
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* and no L2 cache to warn of aliased mappings, we must force an
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@ -1635,12 +1634,12 @@ pmap_copy_page(src, dst)
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mips_flushcache_allpvh(src);
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/* mips_flushcache_allpvh(dst); */
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}
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#endif /* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
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#endif /* MIPS3_PLUS */
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mips_pagecopy((caddr_t)MIPS_PHYS_TO_KSEG0(dst),
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(caddr_t)MIPS_PHYS_TO_KSEG0(src));
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#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
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#if defined(MIPS3_PLUS) /* XXX mmu XXX */
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/*
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* If we have a virtually-indexed, physically-tagged WB cache,
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* and no L2 cache to warn of aliased mappings, we must force a
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@ -1656,7 +1655,7 @@ pmap_copy_page(src, dst)
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
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mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
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}
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#endif /* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
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#endif /* MIPS3_PLUS */
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}
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/*
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@ -1882,7 +1881,7 @@ again:
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pv->pv_pmap = pmap;
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pv->pv_next = NULL;
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} else {
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#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
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#if defined(MIPS3_PLUS) /* XXX mmu XXX */
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if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
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/*
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* There is at least one other VA mapping this page.
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@ -1935,7 +1934,7 @@ again:
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}
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#endif /* !MIPS3_NO_PV_UNCACHED */
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}
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#endif /* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
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#endif /* MIPS3_PLUS */
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/*
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* There is at least one other VA mapping this page.
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