handling for phyiscally-indexed caches where the way size is greater than
the page size.
These work fine with pass 1 SB1 cores, so g/c those workarounds.
Much thanks to Chris Demetriou for many suggestions and helping me get
my head around all this.
asm code which can be built easily in old-ABI and new-ABI environemnts.
In old-ABI, they map to t4-t7, and in new-ABI, they map to a4-a7. This
means that t0-t3,ta0-ta3,t8,t9 are available in both ABIs.
Because ta0-ta3 overlap with arg regs (albeit arg slots which are usually
unused), they should be used only if t0-t3,t8,t9 isn't enough.
- 0x55 for NEC Vr5500. ISA might be MIPS64.
- 0x38 for Toshiba TX79. This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space. Any of pointer related
registers have 32bit.
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.
- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()
Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.
Tested on r3k with and without SOFTFLOAT enabled.
and rename TLB_SHUTDOWN and SOFT_RESET to TS and SR (the abbreviations
in the MIPS documentation).
XXX: this file really needs to be cleaned up one day...
simonb