Commit Graph

14 Commits

Author SHA1 Message Date
thorpej 4616eedacf Document exactly what the problem with TCP/UDP checksum offloading is. 2002-07-14 01:34:00 +00:00
thorpej bc09351189 And thus spake the manual...
When initializing a TCP/IP context descriptor, even if a checksum
offload feature is not going to be used, the IPCSS and TUCSS fields
must be initialized.
2002-07-14 01:12:28 +00:00
thorpej baecca774e * Shuffle the TODO list a bit.
* Fix outbound IPv4 header checksums (missing add of an offset).
* When enabling Rx TCP/UDP checksum offload, make sure that IPv4
  header checksum Rx offload is enabled on the chip, as well.
2002-07-09 21:05:03 +00:00
thorpej 77ef1df52c Don't use internal names to identify chips. Add types for the
i82540, i82545, and i82546 (but don't match them yet).
2002-07-09 19:47:46 +00:00
thorpej 297ae331d6 Make a few performance tweaks:
* Bump the number of Rx descriptors from 128 to 256.
* Don't use a sliding Tx interrupt window.  Instead, just do reap-behind
  when we have <= 1/8 of our available descriptors in wm_start().
* Don't use Tx Queue Empty interrupts, and always set the Tx Interrupt
  Delay bit in the Tx descriptor.
* In wm_intr(), always call wm_rxintr() and wm_txintr(), regardless of
  their respective ISR bits being set.  We're here, might as well do some
  work.
* Adjust the Tx and Rx interrupt delay timer values.  New values from
  Intel's driver for FreeBSD via Allen Briggs.

With these changes, NetBSD can sustain > 900Mb/s userland to userland
*without* using TCP checksum offload using Intel PRO/1000 XT cards.
2002-07-09 14:52:37 +00:00
thorpej 3e669d3bca * Increase the number of Tx job queue entries from 32 to 64.
* Garbage-collect some unused stuff.
* Make the Tx window slide along the Tx job queue space, not the
  Tx descriptor space.  We are more likely to run low on DMA maps
  than we are hardware descriptors.
2002-05-09 01:00:12 +00:00
thorpej 3ce23a4ac6 * Instrument the number of times we force a Tx interrupt.
* When forcing an interrupt, make sure that interrupt-delay-enable is
  cleared (necessary with last change to make sure it's set for all
  descriptors).
* Crank up the Transmit Interrupt Delay Value to 1024 * 1.024 msec.  We
  really want these to be deferred.
2002-05-09 00:41:06 +00:00
thorpej 88f6c3663b Don't set WTX_TCPIP_CMD_TCP or WTX_TCPIP_CMD_IP in the TCP/IP context
descriptor.  Those are apparently only valid if using the Cordova's
"segmentation offload" feature.
2002-05-08 21:43:10 +00:00
thorpej d680cf3220 * Make sure the interrupt-delay bit gets set on ALL descriptors,
except for the one we want to force a Tx interrupt.
* Tweak the Tx descriptor accounting a little.
2002-05-08 21:22:20 +00:00
thorpej 3992641218 Implement a cache for the outbound IP/TCP/UDP checksum offload
context.
2002-05-08 19:00:27 +00:00
thorpej 935179d022 * Account for the descriptor consumed by the Tx checksum offload
context setup.
* Implement Matt Thomas's sliding Tx interrupt window algorithm,
  forcing an interrupt when the Tx desc list is 2/3 consumed.
* Use the Report Packet Sent interrupt, rather than Report Status,
  since we use the Tx descriptor to count Tx errors.
2002-05-08 17:53:28 +00:00
thorpej 84fbb01984 Fix a comment. 2002-05-02 16:34:47 +00:00
thorpej c115365b50 * Deal with errata on the i82542 and i82543 chips: The size of the
transmit and receive descriptor rings is limited to 256 descriptors.
  So, set the if_snd queue length to 256 to let the upper layers queue
  lots of packets, and let the driver handle up to 32 of them at a time.
  (We should probably make this change to most Ethernet drivers, since
  it actually saves some resources.)
* Increase the number of Tx DMA segments from 8 to 16.
* Clean up the way we count "how many times did I get a packet with N
  DMA segments".
* Add a missing htole32() in wm_tx_cksum().
* Don't set both RS and RPS in the last Tx descriptor of a packet; just
  use RS.
* Add some more information to the watchdog message.
2002-05-02 16:33:27 +00:00
thorpej 5f0f48a9f2 Device driver for the Intel i82542, i82542, and i82544 Gigabit
Ethernet interfaces.
2002-03-28 04:54:35 +00:00