Make a few performance tweaks:
* Bump the number of Rx descriptors from 128 to 256. * Don't use a sliding Tx interrupt window. Instead, just do reap-behind when we have <= 1/8 of our available descriptors in wm_start(). * Don't use Tx Queue Empty interrupts, and always set the Tx Interrupt Delay bit in the Tx descriptor. * In wm_intr(), always call wm_rxintr() and wm_txintr(), regardless of their respective ISR bits being set. We're here, might as well do some work. * Adjust the Tx and Rx interrupt delay timer values. New values from Intel's driver for FreeBSD via Allen Briggs. With these changes, NetBSD can sustain > 900Mb/s userland to userland *without* using TCP checksum offload using Intel PRO/1000 XT cards.
This commit is contained in:
thorpej
parent
743c37bcb0
commit
297ae331d6
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@ -1,4 +1,4 @@
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/* $NetBSD: if_wm.c,v 1.9 2002/05/09 01:00:12 thorpej Exp $ */
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/* $NetBSD: if_wm.c,v 1.10 2002/07/09 14:52:37 thorpej Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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@ -121,6 +121,7 @@ int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK;
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#define WM_IFQUEUELEN 256
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#define WM_TXQUEUELEN 64
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#define WM_TXQUEUELEN_MASK (WM_TXQUEUELEN - 1)
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#define WM_TXQUEUE_GC (WM_TXQUEUELEN / 8)
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#define WM_NTXDESC 256
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#define WM_NTXDESC_MASK (WM_NTXDESC - 1)
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#define WM_NEXTTX(x) (((x) + 1) & WM_NTXDESC_MASK)
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@ -129,10 +130,10 @@ int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK;
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/*
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* Receive descriptor list size. We have one Rx buffer for normal
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* sized packets. Jumbo packets consume 5 Rx buffers for a full-sized
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* packet. We allocate 128 receive descriptors, each with a 2k
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* buffer (MCLBYTES), which gives us room for 25 jumbo packets.
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* packet. We allocate 256 receive descriptors, each with a 2k
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* buffer (MCLBYTES), which gives us room for 50 jumbo packets.
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*/
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#define WM_NRXDESC 128
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#define WM_NRXDESC 256
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#define WM_NRXDESC_MASK (WM_NRXDESC - 1)
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#define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK)
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#define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK)
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@ -244,7 +245,6 @@ struct wm_softc {
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int sc_txfree; /* number of free Tx descriptors */
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int sc_txnext; /* next ready Tx descriptor */
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int sc_txwin; /* Tx descriptors since last Tx int */
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int sc_txsfree; /* number of free Tx jobs */
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int sc_txsnext; /* next free Tx job */
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@ -1060,12 +1060,15 @@ wm_start(struct ifnet *ifp)
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sc->sc_dev.dv_xname, m0));
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/* Get a work queue entry. */
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if (sc->sc_txsfree == 0) {
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DPRINTF(WM_DEBUG_TX,
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("%s: TX: no free job descriptors\n",
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sc->sc_dev.dv_xname));
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WM_EVCNT_INCR(&sc->sc_ev_txsstall);
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break;
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if (sc->sc_txsfree < WM_TXQUEUE_GC) {
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wm_txintr(sc);
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if (sc->sc_txsfree == 0) {
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DPRINTF(WM_DEBUG_TX,
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("%s: TX: no free job descriptors\n",
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sc->sc_dev.dv_xname));
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WM_EVCNT_INCR(&sc->sc_ev_txsstall);
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break;
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}
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}
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txs = &sc->sc_txsoft[sc->sc_txsnext];
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@ -1207,12 +1210,6 @@ wm_start(struct ifnet *ifp)
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*/
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sc->sc_txdescs[lasttx].wtx_cmdlen |=
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htole32(WTX_CMD_EOP | WTX_CMD_IFCS | WTX_CMD_RS);
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if (++sc->sc_txwin >= (WM_TXQUEUELEN * 2 / 3)) {
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WM_EVCNT_INCR(&sc->sc_ev_txforceintr);
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sc->sc_txdescs[lasttx].wtx_cmdlen &=
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htole32(~WTX_CMD_IDE);
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sc->sc_txwin = 0;
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}
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#if 0 /* XXXJRT */
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/*
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@ -1365,27 +1362,26 @@ wm_intr(void *arg)
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handled = 1;
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#if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
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if (icr & (ICR_RXDMT0|ICR_RXT0)) {
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DPRINTF(WM_DEBUG_RX,
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("%s: RX: got Rx intr 0x%08x\n",
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sc->sc_dev.dv_xname,
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icr & (ICR_RXDMT0|ICR_RXT0)));
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WM_EVCNT_INCR(&sc->sc_ev_rxintr);
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wm_rxintr(sc);
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}
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if (icr & (ICR_TXDW|ICR_TXQE)) {
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DPRINTF(WM_DEBUG_TX,
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("%s: TX: got TDXW|TXQE interrupt\n",
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sc->sc_dev.dv_xname));
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#ifdef WM_EVENT_COUNTERS
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if (icr & ICR_TXDW)
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WM_EVCNT_INCR(&sc->sc_ev_txdw);
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else if (icr & ICR_TXQE)
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WM_EVCNT_INCR(&sc->sc_ev_txqe);
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#endif
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wm_txintr(sc);
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wm_rxintr(sc);
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#if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
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if (icr & ICR_TXDW) {
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DPRINTF(WM_DEBUG_TX,
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("%s: TX: got TDXW interrupt\n",
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sc->sc_dev.dv_xname));
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WM_EVCNT_INCR(&sc->sc_ev_txdw);
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}
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#endif
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wm_txintr(sc);
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if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) {
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WM_EVCNT_INCR(&sc->sc_ev_linkintr);
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@ -1489,10 +1485,8 @@ wm_txintr(struct wm_softc *sc)
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* If there are no more pending transmissions, cancel the watchdog
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* timer.
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*/
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if (sc->sc_txsfree == WM_TXQUEUELEN) {
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if (sc->sc_txsfree == WM_TXQUEUELEN)
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ifp->if_timer = 0;
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sc->sc_txwin = 0;
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}
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}
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/*
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@ -1839,7 +1833,6 @@ wm_init(struct ifnet *ifp)
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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sc->sc_txfree = WM_NTXDESC;
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sc->sc_txnext = 0;
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sc->sc_txwin = 0;
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sc->sc_txctx_ipcs = 0xffffffff;
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sc->sc_txctx_tucs = 0xffffffff;
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@ -1850,14 +1843,14 @@ wm_init(struct ifnet *ifp)
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CSR_WRITE(sc, WMREG_OLD_TDLEN, sizeof(sc->sc_txdescs));
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CSR_WRITE(sc, WMREG_OLD_TDH, 0);
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CSR_WRITE(sc, WMREG_OLD_TDT, 0);
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CSR_WRITE(sc, WMREG_OLD_TIDV, 1024);
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CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
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} else {
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CSR_WRITE(sc, WMREG_TBDAH, 0);
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CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR(sc, 0));
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CSR_WRITE(sc, WMREG_TDLEN, sizeof(sc->sc_txdescs));
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CSR_WRITE(sc, WMREG_TDH, 0);
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CSR_WRITE(sc, WMREG_TDT, 0);
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CSR_WRITE(sc, WMREG_TIDV, 1024);
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CSR_WRITE(sc, WMREG_TIDV, 128);
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CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
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TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
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@ -1884,7 +1877,7 @@ wm_init(struct ifnet *ifp)
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CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs));
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CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
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CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
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CSR_WRITE(sc, WMREG_OLD_RDTR0, 64 | RDTR_FPD);
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CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
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CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
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CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
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@ -1898,7 +1891,7 @@ wm_init(struct ifnet *ifp)
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CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs));
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CSR_WRITE(sc, WMREG_RDH, 0);
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CSR_WRITE(sc, WMREG_RDT, 0);
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CSR_WRITE(sc, WMREG_RDTR, 64 | RDTR_FPD);
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CSR_WRITE(sc, WMREG_RDTR, 28 | RDTR_FPD);
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}
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for (i = 0; i < WM_NRXDESC; i++) {
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rxs = &sc->sc_rxsoft[i];
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@ -1980,7 +1973,7 @@ wm_init(struct ifnet *ifp)
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* Set up the interrupt registers.
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*/
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CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
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sc->sc_icr = ICR_TXDW | ICR_TXQE | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
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sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
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ICR_RXO | ICR_RXT0;
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if ((sc->sc_flags & WM_F_HAS_MII) == 0)
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sc->sc_icr |= ICR_RXCFG;
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