how many CPU types are configured into the kernel. Then, use this
information to define the CPU predicate macros according to the
following rules:
1. If support for a CPU type is not configured into the kernel,
then the test is always false.
2. Otherwise, if only one CPU type is configured into the kernel,
then the test is always true.
3. Otherwise, we have to reference the cputyp variable.
Use a similar strategy for short-cutting the page size related
definitions.
as (CPU_ISSUN4 || CPU_ISSUN4C) and (CPU_ISSUN4C || CPU_ISSUN4M),
respectively. The compiler can still optimize as desired by expressing
them this way, and it simplifies adding new tests.
While here, just remove CPU_ISSUN4MOR4U; it's not used by anything.
pmap_syncicache. This file uses a ppc feature in a sick and twisted way
to avoid mapping the physical pages used by those routines. It performs
the operations with the MMU disabled but PPC exception save and retstore
the machine state and are invoked with the MMU disabled, this doesn't have
an adverse effect on the system.
Currently only enable for MPC6xx and !OLDPMAP.
isn't perfect (the NetBSD device units must match ARCS device numbers), but
it's better than randomly matching one of the devices. Fixes PR 16584 from
Scott G. Taylor.
use the right places in the trap frame (the 4 segment registers which
get loaded on a rti to VM86 mode) to set them for BIOS calls
(we have never set them to anything but 0 before, so it didn't matter)
- Switch all m68k-based ports over to __HAVE_SYSCALL_INTERN.
- Add systrace glue.
- Define struct mdproc in <m68k/proc.h> instead of <machine/proc.h>.
(They were all defined exactly the same anyway, other than a couple
of the MDP_* flags.)
simple config file option.
Also, don't hard code the endian setting in a header file. Rely instead
on the compiler defining __LITTLE_ENDIAN__ and DTRT as appropriate.
the ECOFF version of boot produced by `objcopy'. Using elf2ecoff make it
work, so use that instead. Also, don't bother stripping the bootblocks on
install (as that confuses strip, at least for the ECOFF one, and since the
build already strips them).
- NeXT label reading support
- SCSI dma fixes
- media support for if_xe.c
Some of these need more cleanup, but at least make SCSI support usable on
the NeXT.
8-bit pseudo color and text modes
still doesn't do anything useful
(It would be easy to attach a wsdisplay, but we have to cooperate with the
PCI or ISA attached VGA drivers. There are open issues.)
directly, using the trampoline only for the return path. Saves a jsr and
movqd insn in the trampoline.
Changes gratuitously ripped off the i386 work for same.
0xc0200000. Tidy up to remove dead comments and code.
Allow more than one L1 entry for the kernel space and use the 'spare'
memory below the kernel code for the initial page tables in the same
way that the iq80310 does.
BIOS calls can be used for device probing etc.
And now it's getting nasty:
The kvm86 code needs a TSS, and it is most convenient to use proc0's
instead of doing some static allocation. (We might reconsider this if
we want to use vm86 for console initialization, ie much earlier.)
For the TSS slot to be allocated, we have to move the call to
i386_proc0_tss_ldt_init() up.
Since the npx code twiddles CR0 the corresponding pcb field must
be synchronized later. It would probably be cleaner to do this in
the npx driver.
8086 machine. Ifff it works, it is much easier and more elegant than
going to real real mode:
-simpler code
-no need for "identity" memory mappings
-easy passing of buffers for bulk data to functions
-some more control
There is no interrupt support ATM, and it lacks a function to access
random virtual memory of the VM. MP issues to consider.
- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()
Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.
Tested on r3k with and without SOFTFLOAT enabled.
Move the trap/vector initialization for MPC6xx ports to mpc6xx_machdep.c
Also move softnet, install_extintr, mapiodev, kvtop. Add common BAT
initialization code.
Add user Altivec support.
Fix calls to OF_call_method in macppc/macppc/machdep.c.
Use ci_fpuproc in cpu_info instead of separate fpuproc.
Add separate syscall.c and defined __HAVE_SYSCALL_INTERN.
MALLOC_NOINLINE, and VNODE_OP_NOINLINE. The exceptions are when they
include another config files that already defines the options, or if
they are for an embedded board, just define a few extra options, and
do not already define PIPE_SOCKETPAIR.
SH-5, meet NetBSD.
Let's hope this is the start of a long and fruitful relationship. :-)
This code, funded by Wasabi Systems, adds initial support for the
Hitachi SuperH(tm) SH-5 cpu architecture to NetBSD.
At the present time, NetBSD/evbsh5 only runs on a SH-5 core simulator
which has no simulated devices other than a simple console. However, it
is good enough to get to the "root device: " prompt.
Device driver support for Real SH-5 Hardware is in place, particularly for
supporting the up-coming Cayman evaluation board, and should be quite
easy to get running when the hardware is available.
There is no in-tree toolchain for this port at this time. Gcc-current has
rudimentary SH-5 support but it is known to be buggy. A working toolchain
was obtained from SuperH to facilitate this port. Gcc-current will be
fixed in due course.
The SH-5 architecture is fully 64-bit capable, although NetBSD/evbsh5 has
currently only been tested in 32-bit mode. It is bi-endian, via a boot-
time option and it also has an "SHcompact" mode in which it will execute
SH-[34] user-land instructions.
For more information on the SH-5, see www.superh.com. Suffice to say it
is *not* just another respin of the SH-[34].
* struct sigacts gets a new sigact_sigdesc structure, which has the
sigaction and the trampoline/version. Version 0 means "legacy kernel
provided trampoline". Other versions are coordinated with machine-
dependent code in libc.
* sigaction1() grows two more arguments -- the trampoline pointer and
the trampoline version.
* A new __sigaction_sigtramp() system call is provided to register a
trampoline along with a signal handler.
* The handler is no longer passed to sensig() functions. Instead,
sendsig() looks up the handler by peeking in the sigacts for the
process getting the signal (since it has to look in there for the
trampoline anyway).
* Native sendsig() functions now select the appropriate trampoline and
its arguments based on the trampoline version in the sigacts.
Changes to libc to use the new facility will be checked in later. Kernel
version not bumped; we will ride the 1.6C bump made recently.
mappings bus_dma(9) states: "In the event that the DMA handle contains
a valid mapping, the mapping will be unloaded via the same mechanism
used by bus_dmamap_unload()." And some drivers do mean to skip the
unload step.
16 SR registers when transitioning between kernel and user. Also, don't
reload the kernel SR(s) on every trap but only on traps from user space.
Instead of loading magic SRs for the kernel, load the kernel SRs from the
kernel_pmap_. This makes trap_subr.S completely ignorant of SR uses and
so they can change with having to change trap_subr.S. Also note that
since the user and kernel get complete SR sets, user VA space can now be
increased to 4GB if desired.
Note that we never use a PTE PP of 0 or 1 (supervisor protection) so the
"key" is basically unused. However, use SR_PRKEY for user space is
conceptionally the right thing to do. Currently the kernel_pmap SR(s) are
ignored but that is going to be fixed shortly.
