discussed with tsutsui@ on port-m68k.
For x68k:
- export ipl2psl_table[] and make it uint16_t
- make makeiplcookie(9) inline
- put PSL_S bit into ipl2psl_table[] rather than adding it in makeiplcookie(9)
- define both IPL_SCHED and IPL_HIGH independently to avoid confusion
suggestion from isaki@ on port-m68k.
For cesfic (compile test only):
- use static splraise4() for splvm() and remove isrcomputeipl() for IPL_VM
because this port supports only one model
- make makeiplcookie(9) return PSL bits via ipl2psl_table[] rather than
ipl indexes
- make ipl2psl_table[] uint16_t rather than int
and use a static and possible highest ipl value (ipl 5) for IPL_VM
so that we can put ipl2psl_table[] conversion into makeiplcookie(9),
which could be called before cpu_configure(9).
Fixes "panic: sbappendaddr" on NFS load.
suggestion from isaki@ on port-m68k.
For mac68k:
- rename mac68k_ipls[] to common ipl2psl_table[]
- make makeiplcookie() return PSL bits via ipl2psl_table[]
rather than IPL_FOO indexes
suggestion from isaki@ on port-m68k.
For sun68k (sun2, sun3 and sun3x):
- export ipl2psl_table[] and make it uint16_t
- make makeiplcookie(9) inline
- put PSL_S bit into ipl2psl_table[] rather than adding it in makeiplcookie(9)
suggestion from isaki@ on port-m68k.
For news68k:
- export ipl2psl_table[] and make it uint16_t
- make makeiplcookie(9) inline
- put PSL_S bit into ipl2psl_table[] rather than adding it in makeiplcookie(9)
- define both IPL_SCHED and IPL_HIGH independently to avoid confusion
bank registers from the PCI host bridge. Previously the RAM size was
hardcoded to 64MB.
Also fill out ibm82660reg.h with more definitions from the PowerPC to
PCI Bridge and Memory Controller User's Manual.
Many thanks to Tim Rightnour for helping with this patch.
PR port-hpcarm/38591
XXX: There is still a hard hang that I've seen on both shark and hpcarm in
the process exit path; I don't know much beyond that yet.
