Automatically detect the amount of installed RAM by reading the memory
bank registers from the PCI host bridge. Previously the RAM size was hardcoded to 64MB. Also fill out ibm82660reg.h with more definitions from the PowerPC to PCI Bridge and Memory Controller User's Manual. Many thanks to Tim Rightnour for helping with this patch.
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mjf
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.10 2008/05/22 20:56:24 rjs Exp $ */
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/* $NetBSD: machdep.c,v 1.11 2008/06/14 12:01:28 mjf Exp $ */
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/*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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@ -32,7 +32,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.10 2008/05/22 20:56:24 rjs Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.11 2008/06/14 12:01:28 mjf Exp $");
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#include "opt_compat_netbsd.h"
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@ -69,6 +69,9 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.10 2008/05/22 20:56:24 rjs Exp $");
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#include <powerpc/oea/bat.h>
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#include <arch/powerpc/pic/picvar.h>
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#include <arch/powerpc/include/pio.h>
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#include <dev/pci/pcivar.h>
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#include <dev/ic/ibm82660reg.h>
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#include <dev/cons.h>
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@ -87,29 +90,49 @@ void
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initppc(u_long startkernel, u_long endkernel, u_int args, void *btinfo)
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{
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uint32_t sa, ea, banks;
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u_long memsize = 0;
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pcitag_t tag;
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/*
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* Set memory region
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* Set memory region by reading the memory size from the PCI
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* host bridge.
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*/
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{
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u_long memsize;
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#if 0
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/* Get the memory size from the PCI host bridge */
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tag = genppc_pci_indirect_make_tag(NULL, 0, 0, 0);
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pci_read_config_32(0, 0x90, &ea);
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if(ea & 0xff00)
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memsize = (((ea >> 8) & 0xff) + 1) << 20;
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else
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memsize = ((ea & 0xff) + 1) << 20;
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#else
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memsize = 64 * 1024 * 1024; /* 64MB hardcoded for now */
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#endif
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out32rb(PCI_MODE1_ADDRESS_REG, tag | IBM_82660_MEM_BANK0_START);
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sa = in32rb(PCI_MODE1_DATA_REG);
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out32rb(PCI_MODE1_ADDRESS_REG, tag | IBM_82660_MEM_BANK0_END);
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ea = in32rb(PCI_MODE1_DATA_REG);
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/* Which memory banks are enabled? */
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out32rb(PCI_MODE1_ADDRESS_REG, tag | IBM_82660_MEM_BANK_ENABLE);
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banks = in32rb(PCI_MODE1_DATA_REG) & 0xFF;
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/* Reset the register for the next call. */
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out32rb(PCI_MODE1_ADDRESS_REG, 0);
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if (banks & IBM_82660_MEM_BANK0_ENABLED)
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memsize += IBM_82660_BANK0_ADDR(ea) - IBM_82660_BANK0_ADDR(sa) + 1;
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if (banks & IBM_82660_MEM_BANK1_ENABLED)
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memsize += IBM_82660_BANK1_ADDR(ea) - IBM_82660_BANK1_ADDR(sa) + 1;
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if (banks & IBM_82660_MEM_BANK2_ENABLED)
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memsize += IBM_82660_BANK2_ADDR(ea) - IBM_82660_BANK2_ADDR(sa) + 1;
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if (banks & IBM_82660_MEM_BANK3_ENABLED)
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memsize += IBM_82660_BANK3_ADDR(ea) - IBM_82660_BANK3_ADDR(sa) + 1;
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memsize <<= 20;
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physmemr[0].start = 0;
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physmemr[0].size = memsize & ~PGOFSET;
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availmemr[0].start = (endkernel + PGOFSET) & ~PGOFSET;
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availmemr[0].size = memsize - availmemr[0].start;
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physmemr[0].start = 0;
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physmemr[0].size = memsize & ~PGOFSET;
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availmemr[0].start = (endkernel + PGOFSET) & ~PGOFSET;
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availmemr[0].size = memsize - availmemr[0].start;
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}
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avail_end = physmemr[0].start + physmemr[0].size; /* XXX temporary */
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: pci_machdep.h,v 1.5 2008/04/28 20:23:26 martin Exp $ */
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/* $NetBSD: pci_machdep.h,v 1.6 2008/06/14 12:01:28 mjf Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -48,4 +48,9 @@ void ibmnws_pci_get_chipset_tag(pci_chipset_tag_t pc);
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* NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
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*/
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extern struct powerpc_bus_dma_tag pci_bus_dma_tag;
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#define PCI_MODE1_ENABLE 0x80000000UL
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#define PCI_MODE1_ADDRESS_REG (PREP_BUS_SPACE_IO + 0xcf8)
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#define PCI_MODE1_DATA_REG (PREP_BUS_SPACE_IO + 0xcfc)
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#endif
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@ -59,12 +59,6 @@
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciconf.h>
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#define PCI_MODE1_ENABLE 0x80000000UL
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#define PCI_MODE1_ADDRESS_REG (PREP_BUS_SPACE_IO + 0xcf8)
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#define PCI_MODE1_DATA_REG (PREP_BUS_SPACE_IO + 0xcfc)
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#define PCI_CBIO 0x10
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void
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ibmnws_pci_get_chipset_tag_indirect(pci_chipset_tag_t pc)
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{
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@ -1,4 +1,4 @@
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/* $NetBSD: ibm82660reg.h,v 1.2 2008/04/28 20:23:50 martin Exp $ */
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/* $NetBSD: ibm82660reg.h,v 1.3 2008/06/14 12:01:28 mjf Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -36,15 +36,97 @@
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* Also known as a Lanai/Kauai.
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*/
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/* Memmory Bank Starting Addresses */
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#define IBM_82660_MEM_BANK0_START 0x80
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#define IBM_82660_MEM_BANK1_START 0x81
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#define IBM_82660_MEM_BANK2_START 0x82
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#define IBM_82660_MEM_BANK3_START 0x83
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#define IBM_82660_MEM_BANK4_START 0x84
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#define IBM_82660_MEM_BANK5_START 0x85
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#define IBM_82660_MEM_BANK6_START 0x86
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#define IBM_82660_MEM_BANK7_START 0x87
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/* Memory Bank Extended Starting Addresses */
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#define IBM_82660_MEM_BANK0_EXTSTART 0x88
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#define IBM_82660_MEM_BANK1_EXTSTART 0x89
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#define IBM_82660_MEM_BANK2_EXTSTART 0x8A
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#define IBM_82660_MEM_BANK3_EXTSTART 0x8B
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#define IBM_82660_MEM_BANK4_EXTSTART 0x8C
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#define IBM_82660_MEM_BANK5_EXTSTART 0x8D
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#define IBM_82660_MEM_BANK6_EXTSTART 0x8E
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#define IBM_82660_MEM_BANK7_EXTSTART 0x8F
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/* Memory Bank Ending Addresses */
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#define IBM_82660_MEM_BANK0_END 0x90
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#define IBM_82660_MEM_BANK1_END 0x91
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#define IBM_82660_MEM_BANK2_END 0x92
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#define IBM_82660_MEM_BANK3_END 0x93
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#define IBM_82660_MEM_BANK4_END 0x94
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#define IBM_82660_MEM_BANK5_END 0x95
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#define IBM_82660_MEM_BANK6_END 0x96
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#define IBM_82660_MEM_BANK7_END 0x97
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/*
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* Helper functions for working with the Memory Bank
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* Start/End Address registers.
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*/
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#define IBM_82660_BANK0_ADDR(x) ((x) & 0xFF)
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#define IBM_82660_BANK1_ADDR(x) (((x) & 0xFF00) >> 8)
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#define IBM_82660_BANK2_ADDR(x) (((x) & 0xFF0000) >> 16)
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#define IBM_82660_BANK3_ADDR(x) (((x) & 0xFF000000) >> 24)
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/* Memory Bank Extended Ending Addresses */
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#define IBM_82660_MEM_BANK0_EXTEND 0x98
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#define IBM_82660_MEM_BANK1_EXTEND 0x99
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#define IBM_82660_MEM_BANK2_EXTEND 0x9A
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#define IBM_82660_MEM_BANK3_EXTEND 0x9B
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#define IBM_82660_MEM_BANK4_EXTEND 0x9C
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#define IBM_82660_MEM_BANK5_EXTEND 0x9D
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#define IBM_82660_MEM_BANK6_EXTEND 0x9E
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#define IBM_82660_MEM_BANK7_EXTEND 0x9F
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#define IBM_82660_MEM_BANK_ENABLE 0xA0
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#define IBM_82660_MEM_BANK0_ENABLED 0x01
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#define IBM_82660_MEM_BANK1_ENABLED 0x02
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#define IBM_82660_MEM_BANK2_ENABLED 0x04
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#define IBM_82660_MEM_BANK3_ENABLED 0x08
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#define IBM_82660_MEM_TIMING_1 0xA1
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#define IBM_82660_MEM_TIMING_2 0xA2
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/* Memory Bank Addressing Modes */
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#define IBM_82660_MEM_BANK01_ADDR_MODE 0xA4 /* Bank 0 and 1 */
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#define IBM_82660_MEM_BANK23_ADDR_MODE 0xA5 /* Bank 2 and 3 */
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#define IBM_82660_MEM_BANK45_ADDR_MODE 0xA6 /* Bank 4 and 5 */
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#define IBM_82660_MEM_BANK67_ADDR_MODE 0xA7 /* Bank 6 and 7 */
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#define IBM_82660_CACHE_STATUS 0xB1
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#define IBM_82660_CACHE_STATUS_L1_EN 0x01
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#define IBM_82660_CACHE_STATUS_L2_EN 0x02
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#define IBM_82660_RAS_WATCHDOG_TIMER 0xB6
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#define IBM_82660_SINGLEBIT_ERR_CNTR 0xB8
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#define IBM_82660_SINGLEBIT_ERR_LEVEL 0xB9
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/* Bridge Options */
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#define IBM_82660_OPTIONS_1 0xBA
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#define IBM_82660_OPTIONS_1_MCP 0x01
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#define IBM_82660_OPTIONS_1_TEA 0x02
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#define IBM_82660_OPTIONS_1_ISA 0x04
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#define IBM_82660_OPTIONS_2 0xBB
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#define IBM_82660_ERR_ENABLE_1 0xC0
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#define IBM_82660_ERR_STATUS_1 0xC1
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#define IBM_82660_CPU_ERR_STATUS 0xC3
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#define IBM_82660_ERR_ENABLE_2 0xC4
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#define IBM_82660_ERR_STATUS_2 0xC5
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#define IBM_82660_PCI_ERR_STATUS 0xC7
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#define IBM_82660_OPTIONS_3 0xD4
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#define IBM_82660_OPTIONS_3_ECC 0x01
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#define IBM_82660_OPTIONS_3_DRAM 0x04
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