This is a completely rewritten scsipi_xfer execution engine, and the
associated changes to HBA drivers. Overview of changes & features:
- All xfers are queued in the mid-layer, rather than doing so in an
ad-hoc fashion in individual adapter drivers.
- Adapter/channel resource management in the mid-layer, avoids even trying
to start running an xfer if the adapter/channel doesn't have the resources.
- Better communication between the mid-layer and the adapters.
- Asynchronous event notification mechanism from adapter to mid-layer and
peripherals.
- Better peripheral queue management: freeze/thaw, sorted requeueing during
recovery, etc.
- Clean separation of peripherals, adapters, and adapter channels (no more
scsipi_link).
- Kernel thread for each scsipi_channel makes error recovery much easier
(no more dealing with interrupt context when recovering from an error).
- Mid-layer support for tagged queueing: commands can have the tag type
set explicitly, tag IDs are allocated in the mid-layer (thus eliminating
the need to use buggy tag ID allocation schemes in many adapter drivers).
- support for QUEUE FULL and CHECK CONDITION status in mid-layer; the command
will be requeued, or a REQUEST SENSE will be sent as appropriate.
Just before the merge syssrc has been tagged with thorpej_scsipi_beforemerge
resulting in a blank screen when f.e. a setcursor ioctl was called
after the screenblanker had enabled the screen again ... the actual
switching on was then never performed at VSYNC.
A simple |= instead of = does the trick ... just leave the other bits
on please :)
saves about 2.2MB under /usr/include/dev/. Discussed on tech-kern@
recently.
I HOPE to get the list right. The headers I left in are ones
used for MI tools and those whose usage I discovered by grep over tree sources.
Feel free to put needed includes back in if you encounter anything which
should not be removed from lists.
- video base register value brings different scanline starting address
of framebuffer depending on VRAM chip column size.
many other issues left unsolved.
- text rendered in incorrect colours.
- acceleration codes should be reimplemented from scratch.
than the preivous code. It can show readable characters on screen.
Tested only with 32bpp model of PMAGD opion card. Need more work for 8bpp.
- 2D accelleration will be revamped to ultilize SFBplus features.
- there seems much mulfunctionness in 32bpp codes of /sys/dev/rasops/.
Need to rectify every corners.
at tcds in files.alpha for now, and add a new `xasc at tcds' to files.pmax.
after pmax has moved fully to MI scsi (and `asc' is MI scsi), we should move
the device asc, etc., lines to files.tc.
an unaligned buffer. The last word of the buffer was not getting flushed
if the buffer was unaligned and fit in a single DMA segment. Now dump(8)
works on both MIPS1 and MIPS3 DECstations.
and the buffer is not 8-byte aligned, it leaves a partial transfer in the
SDRx registers. This could cause data corruption in dump(8) because the
read-ahead buffers are allocated on a non-aligned address. When the read
DMA transfer is interrupted and the current DMA position is not aligned,
call the dma_end() routine to flush the SDRx register contents to the
buffer.
stored in device softc. rasops_cmap[] array is orginazed in 256
iteration of 3 byte long RBG triplet, which does not match with
struct wsdisplay_cmap design.
