for a boot device type; this gets the boot.ip32 booting a kernel off disk.
While here remove some unrolled string compares in favor of strncmp() to
make code more readable.
of KSEG0/1 mappable PCI window (the MEG_ALIGN macro was aligning to *16* MB
instead of *1* MB due to an extra 0 in the round-to constant). Also, allow
the PCI code to fix up all functions of a multifunction device; both from
Chris Sekiya, with a bit of massaging by me.
store absolute year rather than an offset -- this means the clock is now
consitent across the ARCS PROM, IRIX and NetBSD.
XXX: This attachment is now a mismoner, since it's a Dallas Semi RTC, not
a Motorola RTC. Should be renamed.
a buffer long enouth, with the padding bytes initialised.
Also pad to ETHER_MIN_LEN - ETHER_CRC_LEN, not ETHER_MIN_LEN (padded frames
were 4 bytes too long).
external cache enable bit -- this allows software to enable or disable the
(external) L2 cache on the R5k and Rm527x and the (external) L3 cache on
the Rm7k. If the (external) cache is disabled, treat it as if there were
no cache for the purposes of the cache setup code.
Also, update sgimips code to use the new name.
cd ${KERNSRCDIR}/${KERNARCHDIR}/compile && ${PRINTOBJDIR}
This is far simpler than the previous system, and more robust with
objdirs built via BSDOBJDIR.
The previous method of finding KERNOBJDIR when using BSDOBJDIR by
referencing _SRC_TOP_OBJ_ from another directory was extremely
fragile due to the depth first tree walk by <bsd.subdir.mk>, and
the caching of _SRC_TOP_OBJ_ (with MAKEOVERRIDES) which would be
empty on the *first* pass to create fresh objdirs.
This change requires adding sys/arch/*/compile/Makefile to create
the objdir in that directory, and descending into arch/*/compile
from arch/*/Makefile. Remove the now-unnecessary .keep_me files
whilst here.
Per lengthy discussion with Andrew Brown.
pass in an interrupt handle (which is currently to the CRIME interrupt the
device is attached to) so the interrupt handlers know which device was the
one looking for attention.
While here, fix up PCI interrupt routing for both the on-board devices and
the PCI slots -- even though there is only one PCI slot in the chasis, the
hardware can accomodate up to three and provides an interrupt mapping for
all the PCI interrupt pins for both the internal SCSI & PCI slot and the
two "extra" slots.
thorpej