NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.
* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).
* Garbage-collect "ofpci" and "ofppb" from the sparc64 port.
pci_attach_args *" instead of from four separate parameters which in
all cases were extracted from the same "struct pci_attach_args".
This both simplifies the driver api, and allows for alternate PCI
interrupt mapping schemes, such as one using the tables described in
the Intel Multiprocessor Spec which describe interrupt wirings for
devices behind pci-pci bridges based on the device's location rather
the bridge's location.
Tested on alpha and i386; welcome to 1.5Q
(`SUNW,sabre') for now, and it doesn't really quite work there yet anyway.
the bus space/dma code is cloned from the sbus driver. the IOMMU code also
is cloned from the sbus code, but separated out into iommu.c so that we can
share it with the sbus driver. hopefully, much of the bus space/dma code
can also be re-shared with the sbus driver and the ebus driver but for now
these copies will do.
support for the real UltraSPARC PCI (`SUNW,psycho') is unwritten, though
most of this code is shared with it.
we can probe PCI config space and try to configue devices, but interrupts
don't work yet...
eeh