interrupt code for the IQ80310 board support package.
XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.
Those for the SA-1100 and SA-1110 are from Intel's documentation.
The mapping for the SA-110 is from various sources on the net, since Intel
don't seem to document it.
Also, change the layout of the maps to have four steppings per line,
so they aren't quite so unwieldy.
cores.
* For i80200 Step-A0 and Step-A1, set dcache_inv_range to
xscale_cache_purgeD_rng to work around a bug where a D$
"invalidate by address" doesn't properly clear the dirty
bits on the cache block (i80200 errata item #25).
* Track which process (XXX really, vmspace) owns the mapping. When
we sync the map, if the mapping doesn't belong to the kernel or to
the current process (XXX really, vmspace), then no cache fobbing
is necessary, since the cache is Wb-Inv'd on context switch (XXX need
to revisit this when we support FCSE).
* Be smarter about which cache operation we do when sync'ing the map:
- PREREAD -- Invalidate D$ (XXX right now, we actually do Wb-Inv)
- PREWRITE -- Write-back D$ (note, we do NOT invalidate here)
- PREREAD|PREWRITE -- Wb-Inv D$
More work is needed here. In particular, a version for CPUs
with write-through caches should be provided, to eliminate
the write-back steps (which are noops on such CPUs, but skipping
two branches would be nice).
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:
icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range
dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range
idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range
Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.
use 2 adjacent cache-size areas for global cache clean, alternating
between the two of them on each call. Without this, D-cache blocks
aren't evicted properly, and no one seems to know why.
1) Add defparam XSCALE_CCLKCFG to define a parameter for the
CCLKCFG register. Default it to '9' on the IQ80310.
2) Add a sleep call to the xscale CPU function vector (replacing
the nullop) which should drop the CPU into "idle" mode when
cpu_switch finds nothing on the run queues.
by SWI numbers above 0x9f0000, but we re-map them down to somewhere just
after the end of the usual syscall range, since NetBSD doesn't handle
sparse syscall arrays well.
The only syscall I've actually implemented in this range is cacheflush(),
which was previously being mapped to fork(), causing ... interesting results.
swi_handler() does stuff that all SWIs will need, then calls
curproc->p_emul->e_syscall.
syscall() handles native NetBSD system calls.
linux_syscall() handles Linux system calls.
Also update the funcs in arm32_machdep.c that create the entries so that on cats they expect the 2 pagetables to be contiguous, note this means that for now cats is special cased in lots of funcs. I'll tidy this up to something a bit more sane soon, to avoid the multitude of #ifndef cats that I had to sprinkle in.
Note that this leaves a few inconsistencies (no more than we already had though) eg initarm is now prototyped in arm32/machdep.h, however only cats currently makes use of that header.
chris