similar design and code by Jason Thorpe and Jonathan Stone.
NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.
mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.
mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.
mips/include/mips1_pte.h:
mips1 TLB bit definitions.
mips/include/mips3_pte.h:
mips3 TLB bit definitions.
mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.
mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.
mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.
mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)
mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.
mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().
pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
* Move mips-I pte (TLBlo) definitions from pmax/include/pte.h
to mips/include/mips1_pte.h
* Move mips-III pte (TLBlo) definitions from pica/include/pte.h
to mips/include/mips3_pte.h
* Add new mips/include/pte.h, which includes exactly one of
mips1_pte.h or mips3_pte.h (which still have namespace collisions),
depending on "options MIPS1" or "options MIPS3". (hack).
Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h
* Add macro PTE_TO_PADDR() to hide the different hardware TLB formats
when mapping from pte to physical address.
* Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III
tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in
the kernel pmap.)
* Use macros (not direct TLB frobbing) in mips/trap.c, to make it
mips-1/mips-III indepenndet.
* Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
jonathan