the controller/SCSI bus.
* Implement controller/SCSI bus reset on SGI HPC3 SCSI using the
"channel reset" bit in the SCSI DMA channel control register.
- Full support for SCSI-2 Tagged commands (enabled by default)
- Implement save and restore datapointer messages
- Formalize interface between MI and MD drivers.
- decouple interface between MD driver and DMA routines
- Use scsipi layer where appropriate (Tags, Sync Negotiations etc)
- control blocks stored using kernel pool(9) functions
- evcnt(9) compliant counters
- Enable advanced features on later WD33c93 chips.
(Identify message out phase is hardware assisted)
- Improved timeout support (one per active control block)
- Improved MESG_IN and MESG_OUT handling
- Start to tidy up debugging output
- Numerous bug fixes and cleanups throughout
Changes are based largely on the NCR53c9x MI driver for ideas on
how to DTRT.
Based on mvme68k and Atari drivers for the same chipset with the
addition of bus_space support. Attempts have been made to seperate out the
machine dependent dma components and more work is required in this area.
Tested on SGI R4K Indy, but has little testing on other platforms.
thorpej