Complete overhaul of WD33c93 SCSI driver
- Full support for SCSI-2 Tagged commands (enabled by default) - Implement save and restore datapointer messages - Formalize interface between MI and MD drivers. - decouple interface between MD driver and DMA routines - Use scsipi layer where appropriate (Tags, Sync Negotiations etc) - control blocks stored using kernel pool(9) functions - evcnt(9) compliant counters - Enable advanced features on later WD33c93 chips. (Identify message out phase is hardware assisted) - Improved timeout support (one per active control block) - Improved MESG_IN and MESG_OUT handling - Start to tidy up debugging output - Numerous bug fixes and cleanups throughout Changes are based largely on the NCR53c9x MI driver for ideas on how to DTRT.
This commit is contained in:
wdk
parent
9a07d795e3
commit
de81761c50
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@ -1,4 +1,4 @@
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/* $NetBSD: hpcdma.h,v 1.1 2001/08/19 03:16:21 wdk Exp $ */
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/* $NetBSD: hpcdma.h,v 1.2 2001/11/10 07:32:42 wdk Exp $ */
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/*
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* Copyright (c) 2001 Wayne Knowles
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@ -36,8 +36,8 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SGIMIPS_BUS_DMA_H
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#define _SGIMIPS_BUS_DMA_H
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#ifndef _SGIMIPS_HPC_DMA_H
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#define _SGIMIPS_HPC_DMA_H
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#include <machine/bus.h>
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@ -47,13 +47,15 @@ struct hpc_dma_softc {
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bus_dma_tag_t sc_dmat;
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u_int32_t sc_flags;
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#define HPC_DMA_ACTIVE 0x80
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#define HPC_DMA_READ 0x20
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#define HPCDMA_READ 0x20 /* direction of transfer */
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#define HPCDMA_LOADED 0x40 /* bus_dmamap loaded */
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#define HPCDMA_ACTIVE 0x80 /* DMA engine is busy */
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u_int32_t sc_dmacmd;
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int sc_ndesc;
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bus_dmamap_t sc_dmamap;
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struct hpc_dma_desc *sc_desc_kva; /* Virtual address */
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struct hpc_dma_desc *sc_desc_pa; /* Physical address */
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ssize_t sc_dlen; /* number of bytes transfered */
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};
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@ -62,4 +64,4 @@ void hpcdma_sglist_create(struct hpc_dma_softc *, bus_dmamap_t);
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void hpcdma_cntl(struct hpc_dma_softc *, u_int32_t);
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void hpcdma_flush(struct hpc_dma_softc *);
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#endif
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#endif /* _SGIMIPS_HPC_DMA_H */
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File diff suppressed because it is too large
Load Diff
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@ -1,4 +1,4 @@
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/* $NetBSD: sbicreg.h,v 1.1 2001/08/19 03:16:22 wdk Exp $ */
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/* $NetBSD: sbicreg.h,v 1.2 2001/11/10 07:32:42 wdk Exp $ */
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/*
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* Copyright (c) 2001 Wayne Knowles
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@ -84,6 +84,9 @@
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#define SBIC_csr 23
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#define SBIC_cmd 24
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#define SBIC_data 25
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#define SBIC_queue_tag 26
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#define SBIC_aux_status 27
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/* sbic_asr is addressed directly */
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/*
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@ -107,9 +110,10 @@
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*/
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#define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 Mhz */
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/* 11 Mhz is invalid */
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/* 11 Mhz is invalid */
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#define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 Mhz */
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#define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 Mhz */
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#define SBIC_ID_RAF 0x20 /* */
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#define SBIC_ID_EHP 0x10 /* Enable host parity */
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#define SBIC_ID_EAF 0x08 /* Enable Advanced Features */
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#define SBIC_ID_MASK 0x07
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@ -304,6 +308,21 @@
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#define SBIC_CMD_RESELECT_SEND 0x0b /* (DT ) lev II */
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#define SBIC_CMD_WAIT_SEL_RECV 0x0c /* (DT ) lev II */
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#define PHASE_MASK 0x07 /* mask for psns/pctl phase */
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#define DATA_OUT_PHASE 0x00
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#define DATA_IN_PHASE 0x01
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#define CMD_PHASE 0x02
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#define STATUS_PHASE 0x03
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#define BUS_FREE_PHASE 0x04
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#define ARB_SEL_PHASE 0x05 /* Fuji chip combines bus arb with sel. */
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#define MESG_OUT_PHASE 0x06
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#define MESG_IN_PHASE 0x07
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#define SCSI_PHASE(reg) ((reg) & PHASE_MASK)
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#define SCSI_STATUS_MASK 0x3e /* Mask unused bits in status byte */
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/* approximate, but we won't do SBT on selects */
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#define sbic_isa_select(cmd) (((cmd) > 0x5) && ((cmd) < 0xa))
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@ -387,6 +406,8 @@ typedef volatile sbic_padded_ind_regmap_t *sbic_regmap_p;
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#define GET_SBIC_cmd(sc,val) sbic_read_reg(sc,SBIC_cmd,val)
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#define SET_SBIC_data(sc,val) sbic_write_reg(sc,SBIC_data,val)
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#define GET_SBIC_data(sc,val) sbic_read_reg(sc,SBIC_data,val)
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#define SET_SBIC_queue_tag(sc,val) sbic_write_reg(sc,SBIC_queue_tag,val)
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#define GET_SBIC_queue_tag(sc,val) sbic_read_reg(sc,SBIC_queue_tag,val)
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#define SBIC_TC_PUT(sc,val) \
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do { \
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@ -411,12 +432,12 @@ typedef volatile sbic_padded_ind_regmap_t *sbic_regmap_p;
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int n = (cmdsize) - 1; \
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char *ptr = (char *)(cmd); \
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sbic_write_reg(regs, SBIC_cdb1, *ptr++); \
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while(n-- > 0) /* (regs)->sbic_value = *ptr++; */ \
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while(n-- > 0) \
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bus_space_write_1((sc)->sc_regt, (sc)->sc_regh, \
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SBIC_VAL, *ptr++); /* XXX write_multi */ \
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} while (0)
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#define GET_SBIC_asr(sc,val) /* (val) = (regs)->sbic_asr */ \
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#define GET_SBIC_asr(sc,val) \
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do { \
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(val) = bus_space_read_1((sc)->sc_regt,(sc)->sc_regh,SBIC_ASR); \
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} while (0)
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@ -424,7 +445,6 @@ typedef volatile sbic_padded_ind_regmap_t *sbic_regmap_p;
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#define WAIT_CIP(sc) \
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do { \
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/* while ((regs)->sbic_asr & SBIC_ASR_CIP) */ \
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while (bus_space_read_1((sc)->sc_regt,(sc)->sc_regh, \
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SBIC_ASR) & SBIC_ASR_CIP) \
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/*nop*/; \
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@ -432,7 +452,7 @@ typedef volatile sbic_padded_ind_regmap_t *sbic_regmap_p;
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/*
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* transmit a byte in programmed I/O mode
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**/
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*/
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#define SEND_BYTE(sc, ch) \
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do { \
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WAIT_CIP(sc); \
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@ -1,4 +1,4 @@
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/* $NetBSD: sbicvar.h,v 1.1 2001/08/19 03:16:22 wdk Exp $ */
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/* $NetBSD: sbicvar.h,v 1.2 2001/11/10 07:32:43 wdk Exp $ */
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/*
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* Copyright (c) 1990 The Regents of the University of California.
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#include <sys/callout.h>
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#include <sys/malloc.h>
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/*
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* DMA chains are used for Scatter-Gather DMA.
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*/
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struct dma_chain {
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int dc_count;
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char *dc_addr;
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};
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#define SBIC_NTARG 8
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#define SBIC_NLUN 8
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#define SBIC_NTAGS 256
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#define SBIC_MAX_MSGLEN 8
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#define SBIC_ABORT_TIMEOUT 2000 /* time to wait for abort */
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#define SBIC_SENSE_TIMEOUT 1000 /* time to wait for sense */
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/*
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* ACB. Holds additional information for each SCSI command Comments: We
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* need a separate scsi command block because we may need to overwrite it
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* with a request sense command. Basicly, we refrain from fiddling with
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* with a request sense command. Basically, we refrain from fiddling with
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* the scsi_xfer struct (except do the expected updating of return values).
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* We'll generally update: xs->{flags,resid,error,sense,status} and
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* occasionally xs->retries.
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*/
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struct sbic_acb {
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TAILQ_ENTRY(sbic_acb) chain;
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struct scsipi_xfer *xs; /* SCSI xfer ctrl block from above */
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int flags; /* Status */
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#define ACB_FREE 0x00
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#define ACB_ACTIVE 0x01
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#define ACB_DONE 0x04
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#define ACB_BBUF 0x10 /* DMA input needs to be copied from bounce */
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#define ACB_DATAIN 0x20 /* DMA direction flag */
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TAILQ_ENTRY(sbic_acb) chain;
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struct scsipi_xfer *xs; /* SCSI xfer ctrl block from above */
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int flags; /* Status */
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#define ACB_FREE 0x00
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#define ACB_ACTIVE 0x01
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#define ACB_READY 0x02 /* ACB is on ready list */
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#define ACB_DONE 0x04
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#define ACB_SENSE 0x08 /* ACB Requesting sense */
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#define ACB_COMPLETE 0x10 /* Disconnected at end of xfer */
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#define ACB_RESET 0x20 /* Require Reset */
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#define ACB_ABORT 0x40 /* Require Abort */
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struct scsi_generic cmd; /* SCSI command block */
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int clen;
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struct dma_chain sc_kv; /* Virtual address of whole DMA */
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u_long sc_tcnt; /* number of bytes for this DMA */
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u_short sc_usedma; /* Internal data for this DMA */
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int timeout;
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struct scsi_generic cmd; /* SCSI command block */
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int clen;
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char *daddr; /* kva for data */
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size_t dleft; /* bytes remaining */
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u_char tag_type; /* TAG Type (0x20-0x22, 0=No Tags) */
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u_char tag_id; /* TAG id number */
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};
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/*
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* probably have been a "per target+lunit" structure, but we'll leave it at
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* this for now. Is there a way to reliably hook it up to sc->fordriver??
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*/
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struct sbic_tinfo {
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int cmds; /* #commands processed */
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int dconns; /* #disconnects */
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int lubusy; /* What local units/subr. are busy? */
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} tinfo_t;
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struct sbic_softc {
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struct device sc_dev;
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struct target_sync {
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u_char state;
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u_char period;
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u_char offset;
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} sc_sync[8];
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u_char target; /* Currently active target */
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u_char lun;
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struct scsipi_channel sc_channel; /* proto for sub devices */
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struct scsipi_adapter sc_adapter;
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/* HPC registers */
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bus_space_tag_t sc_hpct;
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bus_space_handle_t sc_hpch;
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/* HPC external ethernet registers: aka Seeq 8003 registers */
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bus_space_tag_t sc_regt;
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bus_space_handle_t sc_regh;
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bus_dma_tag_t sc_dmat;
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bus_dmamap_t sc_dmamap; /* DMA Map for this transfer */
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void *sc_driver; /* driver specific field */
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struct callout sc_timo_ch;
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/* Lists of command blocks */
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TAILQ_HEAD(acb_list, sbic_acb) free_list,
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ready_list,
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nexus_list;
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struct sbic_acb *sc_nexus; /* current command */
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struct sbic_acb sc_acb[8]; /* the real command blocks */
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struct sbic_tinfo sc_tinfo[8];
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struct scsipi_xfer *sc_xs; /* transfer from high level code */
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u_int32_t sc_flags;
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u_char sc_stat[2];
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u_char sc_msg[7];
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u_long sc_clkfreq;
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u_long sc_tcnt; /* number of bytes transfered */
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u_short sc_usedma; /* used by dma drivers */
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#ifdef DEBUG
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u_short sc_dmatimo; /* dma timeout */
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#endif
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int (*sc_dmasetup) __P((struct sbic_softc *, bus_dmamap_t, int));
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int (*sc_dmago) __P((struct sbic_softc *));
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void (*sc_enintr) __P((struct sbic_softc *));
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void (*sc_dmastop) __P((struct sbic_softc *));
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struct sbic_linfo {
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LIST_ENTRY(sbic_linfo) link;
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time_t last_used;
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int lun;
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int used; /* # slots in use */
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int avail; /* where to start scanning */
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u_char state;
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#define L_STATE_IDLE 0
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#define L_STATE_BUSY 1
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#define L_STATE_ESTAT 2
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struct sbic_acb *untagged;
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struct sbic_acb *queued[SBIC_NTAGS];
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};
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/*
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* sc_flags
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*/
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#define SBICF_ALIVE 0x01 /* controller initialized */
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#define SBICF_DCFLUSH 0x02 /* need flush for overlap after dma finishes */
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#define SBICF_SELECTED 0x04 /* bus is in selected state. */
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#define SBICF_ICMD 0x08 /* Immediate command in execution */
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#define SBICF_BADDMA 0x10 /* controller can only DMA */
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#define SBICF_DMALOADED 0x20 /* bus_dmamap loaded */
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#define SBICF_INTR 0x40 /* SBICF interrupt expected */
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#define SBICF_INDMA 0x80 /* not used yet, DMA I/O in progress */
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struct sbic_tinfo {
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int cmds; /* # of commands processed */
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int dconns; /* # of disconnects */
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/*
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* sync states
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*/
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#define SYNC_START 0 /* no sync handshake started */
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#define SYNC_SENT 1 /* we sent sync request, no answer yet */
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#define SYNC_DONE 2 /* target accepted our (or inferior) settings,
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or it rejected the request and we stay async */
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u_char flags;
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#define T_NEED_RESET 0x01 /* Should send a BUS_DEV_RESET */
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#define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
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#define T_BUSY 0x04 /* Target is busy */
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#define T_SYNCMODE 0x08 /* SYNC mode has been negotiated */
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#define T_NOSYNC 0x10 /* Force ASYNC mode */
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#define T_NODISC 0x20 /* Don't allow disconnect */
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#define T_TAG 0x40 /* Turn on TAG QUEUEs */
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u_char period; /* Period suggestion */
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u_char offset; /* Offset suggestion */
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u_char nextag; /* Next available tag */
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struct sbic_linfo *lun[SBIC_NLUN]; /* LUN list for this target */
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} tinfo_t;
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#define PHASE 0x07 /* mask for psns/pctl phase */
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#define DATA_OUT_PHASE 0x00
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#define DATA_IN_PHASE 0x01
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#define CMD_PHASE 0x02
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#define STATUS_PHASE 0x03
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#define BUS_FREE_PHASE 0x04
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#define ARB_SEL_PHASE 0x05 /* Fuji chip combines arbitration with sel. */
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#define MESG_OUT_PHASE 0x06
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#define MESG_IN_PHASE 0x07
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/* Look up a lun in a tinfo */
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#define TINFO_LUN(t, l) ((t)->lun[(l)])
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#define MSG_CMD_COMPLETE 0x00
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#define MSG_EXT_MESSAGE 0x01
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#define MSG_SAVE_DATA_PTR 0x02
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#define MSG_RESTORE_PTR 0x03
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#define MSG_DISCONNECT 0x04
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#define MSG_INIT_DETECT_ERROR 0x05
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#define MSG_ABORT 0x06
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#define MSG_REJECT 0x07
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#define MSG_NOOP 0x08
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#define MSG_PARITY_ERROR 0x09
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#define MSG_BUS_DEVICE_RESET 0x0C
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#define MSG_IDENTIFY 0x80
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#define MSG_IDENTIFY_DR 0xc0 /* (disconnect/reconnect allowed) */
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#define MSG_SYNC_REQ 0x01
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struct sbic_softc {
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struct device sc_dev;
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#define MSG_ISIDENTIFY(x) ((x) & MSG_IDENTIFY)
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struct scsipi_channel sc_channel; /* proto for sub devices */
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struct scsipi_adapter sc_adapter;
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struct device *sc_child; /* attached scsibus, if any */
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struct callout sc_watchdog;
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void *sc_driver; /* driver specific field */
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int target; /* Currently active target */
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int lun; /* Currently active LUN */
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/* WD33c93 registers */
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bus_space_tag_t sc_regt;
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bus_space_handle_t sc_regh;
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#define STS_CHECKCOND 0x02 /* Check Condition (ie., read sense) */
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#define STS_CONDMET 0x04 /* Condition Met (ie., search worked) */
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#define STS_BUSY 0x08
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#define STS_INTERMED 0x10 /* Intermediate status sent */
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#define STS_EXT 0x80 /* Extended status valid */
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/* Data about the current nexus (updated for every cmd switch) */
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caddr_t sc_daddr; /* Current data pointer */
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size_t sc_dleft; /* Data left to transfer */
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ssize_t sc_tcnt; /* number of bytes transfered */
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/* Lists of command blocks */
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TAILQ_HEAD(acb_list, sbic_acb) ready_list;
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struct sbic_acb *sc_nexus; /* current command */
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struct sbic_tinfo sc_tinfo[8];
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u_short sc_state;
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u_short sc_status;
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int sc_disc; /* current # of active nexus's */
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int sc_flags;
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/* Message stuff */
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u_short sc_msgify; /* Last IDENTIFY message */
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u_short sc_msgout; /* Current message out */
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u_short sc_msgpriq; /* mesg_out queue (bitmap) */
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u_short sc_msgoutq; /* mesg_out queue */
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u_char sc_imsg[SBIC_MAX_MSGLEN];
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u_char sc_omsg[SBIC_MAX_MSGLEN];
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u_char sc_imsglen;
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u_char sc_omsglen;
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/* Static hardware attributes */
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int sc_id; /* SCSI ID for controller */
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int sc_clkfreq; /* wd33c93 clk freq * 10Mhz */
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int sc_chip; /* Chip variation */
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int sc_rev; /* Chip revision */
|
||||
int sc_cfflags; /* Copy of config flags */
|
||||
int sc_maxxfer; /* Maximum transfer size */
|
||||
int sc_minsync; /* Minimum sync period (4ns units) */
|
||||
int sc_maxoffset; /* Maximum sync ofset (bytes) */
|
||||
|
||||
int (*sc_dmasetup) __P((struct sbic_softc *,caddr_t *,
|
||||
size_t *,int,size_t *));
|
||||
int (*sc_dmago) __P((struct sbic_softc *));
|
||||
void (*sc_dmastop) __P((struct sbic_softc *));
|
||||
};
|
||||
|
||||
/* values for sc_flags */
|
||||
#define SBICF_SELECTED 0x01 /* bus is in selected state. */
|
||||
#define SBICF_NODMA 0x02 /* Polled transfer */
|
||||
#define SBICF_INDMA 0x04 /* DMA I/O in progress */
|
||||
#define SBICF_SYNCNEGO 0x08 /* Sync negotiation in progress */
|
||||
#define SBICF_ABORTING 0x10 /* Aborting */
|
||||
|
||||
/* values for sc_state */
|
||||
#define SBIC_UNINITIALIZED 0 /* Driver not initialized */
|
||||
#define SBIC_IDLE 1 /* waiting for something to do */
|
||||
#define SBIC_SELECTING 2 /* SCSI command is arbiting */
|
||||
#define SBIC_RESELECTED 3 /* Has been reselected */
|
||||
#define SBIC_IDENTIFIED 4 /* Has gotten IFY but not TAG */
|
||||
#define SBIC_CONNECTED 5 /* Actively using the SCSI bus */
|
||||
#define SBIC_DISCONNECT 6 /* MSG_DISCONNECT received */
|
||||
#define SBIC_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
|
||||
#define SBIC_ERROR 8 /* Error has occured */
|
||||
#define SBIC_SELTIMEOUT 9 /* Select Timeout */
|
||||
#define SBIC_CLEANING 10 /* Scrubbing ACB's */
|
||||
#define SBIC_BUSRESET 11 /* SCSI RST has been issued */
|
||||
|
||||
/* values for sc_msgout */
|
||||
#define SEND_DEV_RESET 0x0001
|
||||
#define SEND_PARITY_ERROR 0x0002
|
||||
#define SEND_INIT_DET_ERR 0x0004
|
||||
#define SEND_REJECT 0x0008
|
||||
#define SEND_IDENTIFY 0x0010
|
||||
#define SEND_ABORT 0x0020
|
||||
#define SEND_WDTR 0x0040
|
||||
#define SEND_SDTR 0x0080
|
||||
#define SEND_TAG 0x0100
|
||||
|
||||
/* WD33c93 chipset revisions - values for sc_rev */
|
||||
#define SBIC_CHIP_UNKNOWN 0
|
||||
#define SBIC_CHIP_WD33C93 1
|
||||
#define SBIC_CHIP_WD33C93A 2
|
||||
#define SBIC_CHIP_WD33C93B 3
|
||||
|
||||
#define SBIC_CHIP_LIST {"UNKNOWN", "WD33C93", "WD33C93A", "WD33C93B"}
|
||||
|
||||
/*
|
||||
* States returned by our state machine
|
||||
*/
|
||||
#define SBIC_STATE_ERROR -1
|
||||
#define SBIC_STATE_DONE 0
|
||||
#define SBIC_STATE_RUNNING 1
|
||||
#define SBIC_STATE_DISCONNECT 2
|
||||
|
||||
#define SBIC_STATE_ERROR -1
|
||||
#define SBIC_STATE_DONE 0
|
||||
#define SBIC_STATE_RUNNING 1
|
||||
#define SBIC_STATE_DISCONNECT 2
|
||||
#define DEBUG_ACBS 0x01
|
||||
#define DEBUG_INTS 0x02
|
||||
#define DEBUG_CMDS 0x04
|
||||
#define DEBUG_MISC 0x08
|
||||
#define DEBUG_TRAC 0x10
|
||||
#define DEBUG_RSEL 0x20
|
||||
#define DEBUG_PHASE 0x40
|
||||
#define DEBUG_DMA 0x80
|
||||
#define DEBUG_CCMDS 0x100
|
||||
#define DEBUG_MSGS 0x200
|
||||
#define DEBUG_TAGS 0x400
|
||||
#define DEBUG_SYNC 0x800
|
||||
|
||||
#ifdef DEBUG
|
||||
extern int sbic_debug_flags;
|
||||
#define SBIC_DEBUG(level, str) \
|
||||
do { \
|
||||
if (sbic_debug & __CONCAT(DEBUG_,level)) \
|
||||
printf str; \
|
||||
} while (0)
|
||||
#else
|
||||
#define SBIC_DEBUG(level, str)
|
||||
#endif
|
||||
|
||||
struct buf;
|
||||
struct scsipi_xfer;
|
||||
|
|
@ -208,7 +260,7 @@ struct scsipi_xfer;
|
|||
void sbic_minphys __P((struct buf *bp));
|
||||
void sbic_scsi_request __P((struct scsipi_channel *,
|
||||
scsipi_adapter_req_t, void *));
|
||||
void sbicinit __P((struct sbic_softc *));
|
||||
int sbicintr __P((struct sbic_softc *));
|
||||
void sbic_attach __P((struct sbic_softc *));
|
||||
int sbic_intr __P((struct sbic_softc *));
|
||||
|
||||
#endif /* _SBICVAR_H_ */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: wdsc.c,v 1.1 2001/08/19 03:16:22 wdk Exp $ */
|
||||
/* $NetBSD: wdsc.c,v 1.2 2001/11/10 07:32:43 wdk Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Wayne Knowles
|
||||
|
|
@ -38,13 +38,7 @@
|
|||
|
||||
/*
|
||||
* TODO:
|
||||
*
|
||||
* Support for 2nd SCSI controller
|
||||
* evcnt(9) hooks
|
||||
* remove struct dma_chain
|
||||
* dma{setup,stop,go} API similar to NCR93c9x MI driver
|
||||
* improve hpcdma functions
|
||||
* cleanup softc stuff
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
|
|
@ -68,9 +62,17 @@
|
|||
#include <sgimips/hpc/sbicreg.h>
|
||||
#include <sgimips/hpc/sbicvar.h>
|
||||
|
||||
#include <opt_kgdb.h>
|
||||
#include <sys/kgdb.h>
|
||||
|
||||
struct wdsc_softc {
|
||||
struct sbic_softc sc_sbic; /* Must be first */
|
||||
|
||||
struct evcnt sc_intrcnt; /* Interrupt counter */
|
||||
bus_dma_tag_t sc_dmat;
|
||||
bus_dmamap_t sc_dmamap;
|
||||
int sc_flags;
|
||||
#define WDSC_DMA_ACTIVE 0x1
|
||||
#define WDSC_DMA_MAPLOADED 0x2
|
||||
struct hpc_dma_softc sc_hpcdma;
|
||||
};
|
||||
|
||||
|
|
@ -84,8 +86,8 @@ struct cfattach wdsc_ca = {
|
|||
|
||||
extern struct cfdriver wdsc_cd;
|
||||
|
||||
void wdsc_enintr __P((struct sbic_softc *));
|
||||
int wdsc_dmasetup __P((struct sbic_softc *, bus_dmamap_t, int));
|
||||
int wdsc_dmasetup __P((struct sbic_softc *, caddr_t *,size_t *,
|
||||
int, size_t *));
|
||||
int wdsc_dmago __P((struct sbic_softc *));
|
||||
void wdsc_dmastop __P((struct sbic_softc *));
|
||||
int wdsc_dmaintr __P((void *));
|
||||
|
|
@ -101,15 +103,15 @@ int wdsc_scsiintr __P((void *));
|
|||
*/
|
||||
int
|
||||
wdsc_match(pdp, cf, auxp)
|
||||
struct device *pdp;
|
||||
struct cfdata *cf;
|
||||
void *auxp;
|
||||
struct device *pdp;
|
||||
struct cfdata *cf;
|
||||
void *auxp;
|
||||
{
|
||||
struct hpc_attach_args *haa = auxp;
|
||||
struct hpc_attach_args *haa = auxp;
|
||||
|
||||
if (strcmp(haa->ha_name, wdsc_cd.cd_name))
|
||||
return (0);
|
||||
return (1);
|
||||
if (strcmp(haa->ha_name, wdsc_cd.cd_name))
|
||||
return (0);
|
||||
return (1);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -117,134 +119,102 @@ wdsc_match(pdp, cf, auxp)
|
|||
*/
|
||||
void
|
||||
wdsc_attach(pdp, dp, auxp)
|
||||
struct device *pdp, *dp;
|
||||
void *auxp;
|
||||
struct device *pdp, *dp;
|
||||
void *auxp;
|
||||
{
|
||||
struct sbic_softc *sc = (void *)dp;
|
||||
struct wdsc_softc *wdsc = (void *)dp;
|
||||
struct hpc_attach_args *haa = auxp;
|
||||
int err;
|
||||
struct sbic_softc *sc = (void *)dp;
|
||||
struct wdsc_softc *wsc = (void *)dp;
|
||||
struct hpc_attach_args *haa = auxp;
|
||||
int err;
|
||||
|
||||
sc->sc_regt = haa->ha_iot;
|
||||
sc->sc_dmat = haa->ha_dmat;
|
||||
sc->sc_regt = haa->ha_iot;
|
||||
wsc->sc_dmat = haa->ha_dmat;
|
||||
|
||||
if ((err = bus_space_subregion(haa->ha_iot, haa->ha_ioh,
|
||||
if ((err = bus_space_subregion(haa->ha_iot, haa->ha_ioh,
|
||||
HPC_SCSI0_DEVREGS,
|
||||
HPC_SCSI0_DEVREGS_SIZE,
|
||||
&sc->sc_regh)) != 0) {
|
||||
printf(": unable to map WD33C93 regs, err=%d\n", err);
|
||||
goto fail;
|
||||
}
|
||||
printf(": unable to map regs, err=%d\n", err);
|
||||
return;
|
||||
}
|
||||
|
||||
if (bus_dmamap_create(sc->sc_dmat, MAX_DMA_SZ,
|
||||
if (bus_dmamap_create(wsc->sc_dmat, MAX_DMA_SZ,
|
||||
DMA_SEGS, MAX_SEG_SZ, MAX_SEG_SZ,
|
||||
BUS_DMA_WAITOK,
|
||||
&sc->sc_dmamap) != 0) {
|
||||
&wsc->sc_dmamap) != 0) {
|
||||
printf(": failed to create dmamap\n");
|
||||
goto fail;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
hpcdma_init(haa, &wdsc->sc_hpcdma, DMA_SEGS);
|
||||
sc->sc_dmasetup = wdsc_dmasetup;
|
||||
sc->sc_dmago = wdsc_dmago;
|
||||
sc->sc_dmastop = wdsc_dmastop;
|
||||
|
||||
sc->sc_enintr = wdsc_enintr;
|
||||
sc->sc_dmasetup = wdsc_dmasetup;
|
||||
sc->sc_dmago = wdsc_dmago;
|
||||
sc->sc_dmastop = wdsc_dmastop;
|
||||
sc->sc_adapter.adapt_request = sbic_scsi_request;
|
||||
sc->sc_adapter.adapt_minphys = minphys;
|
||||
|
||||
sc->sc_adapter.adapt_dev = &sc->sc_dev;
|
||||
sc->sc_adapter.adapt_nchannels = 1;
|
||||
sc->sc_adapter.adapt_openings = 7;
|
||||
sc->sc_adapter.adapt_max_periph = 1;
|
||||
sc->sc_adapter.adapt_ioctl = NULL;
|
||||
sc->sc_adapter.adapt_minphys = minphys;
|
||||
sc->sc_adapter.adapt_request = sbic_scsi_request;
|
||||
sc->sc_channel.chan_adapter = &sc->sc_adapter;
|
||||
sc->sc_channel.chan_bustype = &scsi_bustype;
|
||||
sc->sc_channel.chan_channel = 0;
|
||||
sc->sc_channel.chan_ntargets = 8;
|
||||
sc->sc_channel.chan_nluns = 8;
|
||||
sc->sc_channel.chan_id = 7;
|
||||
sc->sc_id = 7; /* Host ID = 7 */
|
||||
sc->sc_clkfreq = 200; /* 20MHz Clock */
|
||||
|
||||
printf(": WD33C93 SCSI, target %d\n", sc->sc_channel.chan_id);
|
||||
evcnt_attach_dynamic(&wsc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
|
||||
sc->sc_dev.dv_xname, "intr");
|
||||
|
||||
/*
|
||||
* Controller clock frequency * 10
|
||||
*/
|
||||
sc->sc_clkfreq = 200;
|
||||
|
||||
/*
|
||||
* Initialise the hardware
|
||||
*/
|
||||
sbicinit(sc);
|
||||
|
||||
/* XXX: 1 = IRQ_LOCAL0 + 1 */
|
||||
if ((cpu_intr_establish(1, IPL_BIO, wdsc_scsiintr, sc)) == NULL) {
|
||||
/* XXX: 1 = IRQ_LOCAL0 + 1 */
|
||||
if ((cpu_intr_establish(1, IPL_BIO, wdsc_scsiintr, sc)) == NULL) {
|
||||
printf(": unable to establish interrupt!\n");
|
||||
goto fail;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
(void)config_found(dp, &sc->sc_channel, scsiprint);
|
||||
|
||||
fail:
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable DMA interrupts
|
||||
*/
|
||||
void
|
||||
wdsc_enintr(dev)
|
||||
struct sbic_softc *dev;
|
||||
{
|
||||
dev->sc_flags |= SBICF_INTR;
|
||||
hpcdma_init(haa, &wsc->sc_hpcdma, DMA_SEGS);
|
||||
sbic_attach(sc);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prime the hardware for a DMA transfer
|
||||
*
|
||||
* Requires splbio() interrupts to be disabled by the caller
|
||||
*/
|
||||
int
|
||||
wdsc_dmasetup(dev, dmamap, flags)
|
||||
struct sbic_softc *dev;
|
||||
bus_dmamap_t dmamap;
|
||||
int flags;
|
||||
wdsc_dmasetup(dev, addr, len, datain, dmasize)
|
||||
struct sbic_softc *dev;
|
||||
caddr_t *addr;
|
||||
size_t *len;
|
||||
int datain;
|
||||
size_t *dmasize;
|
||||
{
|
||||
struct hpc_dma_softc *dsc = &((struct wdsc_softc *)dev)->sc_hpcdma;
|
||||
struct sbic_acb *acb = dev->sc_nexus;
|
||||
int s;
|
||||
int count, err;
|
||||
void *vaddr;
|
||||
struct wdsc_softc *wsc = (void *)dev;
|
||||
struct hpc_dma_softc *dsc = &wsc->sc_hpcdma;
|
||||
int count, err;
|
||||
void *vaddr;
|
||||
|
||||
KASSERT((dsc->sc_flags & HPC_DMA_ACTIVE) == 0);
|
||||
KASSERT((wsc->sc_flags & WDSC_DMA_ACTIVE) == 0);
|
||||
|
||||
vaddr = acb->sc_kv.dc_addr;
|
||||
count = acb->sc_kv.dc_count;
|
||||
vaddr = *addr;
|
||||
count = dsc->sc_dlen = *len;
|
||||
if (count) {
|
||||
KASSERT((wsc->sc_flags & WDSC_DMA_MAPLOADED) == 0);
|
||||
|
||||
if (count) {
|
||||
s = splbio();
|
||||
|
||||
/* have dmamap for the transfering addresses */
|
||||
if ((err=bus_dmamap_load(dev->sc_dmat, dev->sc_dmamap,
|
||||
/* Build list of physical addresses for this transfer */
|
||||
if ((err=bus_dmamap_load(wsc->sc_dmat, wsc->sc_dmamap,
|
||||
vaddr, count,
|
||||
NULL /* kernel address */,
|
||||
BUS_DMA_NOWAIT)) != 0)
|
||||
panic("%s: bus_dmamap_load err=%d",
|
||||
dev->sc_dev.dv_xname, err);
|
||||
|
||||
dev->sc_flags |= SBICF_DMALOADED; /* XXX - Move to MD */
|
||||
dev->sc_flags |= SBICF_INTR;
|
||||
panic("%s: bus_dmamap_load err=%d",
|
||||
dev->sc_dev.dv_xname, err);
|
||||
|
||||
hpcdma_sglist_create(dsc, dev->sc_dmamap);
|
||||
hpcdma_sglist_create(dsc, wsc->sc_dmamap);
|
||||
wsc->sc_flags |= WDSC_DMA_MAPLOADED;
|
||||
|
||||
dsc->sc_dmacmd = HPC_DMACTL_ACTIVE; /* XXX - remove tests in MI */
|
||||
if (flags & ACB_DATAIN) {
|
||||
dsc->sc_flags |= HPC_DMA_READ;
|
||||
} else {
|
||||
dsc->sc_dmacmd |= HPC_DMACTL_DIR;
|
||||
dsc->sc_flags &= ~HPC_DMA_READ;
|
||||
}
|
||||
splx(s);
|
||||
}
|
||||
return(count);
|
||||
if (datain) {
|
||||
dsc->sc_dmacmd = HPC_DMACTL_ACTIVE;
|
||||
dsc->sc_flags |= HPCDMA_READ;
|
||||
} else {
|
||||
dsc->sc_dmacmd = HPC_DMACTL_ACTIVE | HPC_DMACTL_DIR;
|
||||
dsc->sc_flags &= ~HPCDMA_READ;
|
||||
}
|
||||
}
|
||||
return(count);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -252,57 +222,64 @@ wdsc_dmasetup(dev, dmamap, flags)
|
|||
*/
|
||||
int
|
||||
wdsc_dmago(dev)
|
||||
struct sbic_softc *dev;
|
||||
struct sbic_softc *dev;
|
||||
{
|
||||
struct hpc_dma_softc *dsc = &((struct wdsc_softc *)dev)->sc_hpcdma;
|
||||
struct wdsc_softc *wsc = (void *)dev;
|
||||
struct hpc_dma_softc *dsc = &wsc->sc_hpcdma;
|
||||
|
||||
if (dev->sc_tcnt == 0) {
|
||||
return(0);
|
||||
}
|
||||
if (dsc->sc_dlen == 0)
|
||||
return(0);
|
||||
|
||||
KASSERT((dsc->sc_flags & HPC_DMA_ACTIVE) == 0);
|
||||
dsc->sc_flags |= HPC_DMA_ACTIVE;
|
||||
KASSERT((wsc->sc_flags & WDSC_DMA_ACTIVE) == 0);
|
||||
KASSERT((wsc->sc_flags & WDSC_DMA_MAPLOADED));
|
||||
|
||||
bus_dmamap_sync(dev->sc_dmat, dev->sc_dmamap, 0, dev->sc_tcnt,
|
||||
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
||||
wsc->sc_flags |= WDSC_DMA_ACTIVE;
|
||||
|
||||
hpcdma_cntl(dsc, dsc->sc_dmacmd); /* Thunderbirds are go! */
|
||||
bus_dmamap_sync(wsc->sc_dmat, wsc->sc_dmamap, 0,
|
||||
wsc->sc_dmamap->dm_mapsize,
|
||||
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
||||
|
||||
return(dev->sc_dmamap->dm_mapsize);
|
||||
hpcdma_cntl(dsc, dsc->sc_dmacmd); /* Thunderbirds are go! */
|
||||
|
||||
return(wsc->sc_dmamap->dm_mapsize);
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop DMA, and disable interrupts
|
||||
* Stop DMA and unload active DMA maps
|
||||
*/
|
||||
void
|
||||
wdsc_dmastop(dev)
|
||||
struct sbic_softc *dev;
|
||||
struct sbic_softc *dev;
|
||||
{
|
||||
struct hpc_dma_softc *dsc = &((struct wdsc_softc *)dev)->sc_hpcdma;
|
||||
struct wdsc_softc *wsc = (void *)dev;
|
||||
struct hpc_dma_softc *dsc = &wsc->sc_hpcdma;
|
||||
|
||||
if (dsc->sc_flags & HPC_DMA_ACTIVE) {
|
||||
if (dsc->sc_flags & HPC_DMA_READ)
|
||||
hpcdma_flush(dsc);
|
||||
hpcdma_cntl(dsc, 0); /* Stop DMA */
|
||||
bus_dmamap_sync(dev->sc_dmat, dev->sc_dmamap, 0,
|
||||
dev->sc_dmamap->dm_mapsize,
|
||||
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
|
||||
dsc->sc_flags &= ~HPC_DMA_ACTIVE;
|
||||
}
|
||||
if (dev->sc_flags & SBICF_DMALOADED)
|
||||
bus_dmamap_unload(dev->sc_dmat, dev->sc_dmamap);
|
||||
if (wsc->sc_flags & WDSC_DMA_ACTIVE) {
|
||||
if (dsc->sc_flags & HPCDMA_READ)
|
||||
hpcdma_flush(dsc);
|
||||
hpcdma_cntl(dsc, 0); /* Stop DMA */
|
||||
bus_dmamap_sync(wsc->sc_dmat, wsc->sc_dmamap, 0,
|
||||
wsc->sc_dmamap->dm_mapsize,
|
||||
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
|
||||
}
|
||||
if (wsc->sc_flags & WDSC_DMA_MAPLOADED)
|
||||
bus_dmamap_unload(wsc->sc_dmat, wsc->sc_dmamap);
|
||||
wsc->sc_flags &= ~(WDSC_DMA_ACTIVE | WDSC_DMA_MAPLOADED);
|
||||
}
|
||||
|
||||
/*
|
||||
* SCSI controller interrupt
|
||||
* WD33c93 SCSI controller interrupt
|
||||
*/
|
||||
int
|
||||
wdsc_scsiintr(arg)
|
||||
void *arg;
|
||||
void *arg;
|
||||
{
|
||||
struct sbic_softc *dev = arg;
|
||||
int found;
|
||||
struct sbic_softc *dev = arg;
|
||||
struct wdsc_softc *wsc = arg;
|
||||
int found;
|
||||
|
||||
found = sbicintr(dev);
|
||||
return(found);
|
||||
found = sbic_intr(dev);
|
||||
if (found)
|
||||
wsc->sc_intrcnt.ev_count++;
|
||||
return(found);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue